作者: AMD
The Versal™ adaptive compute acceleration platforms Control, Interfaces, and Processing System (CIPS) Verification Intellectual Property (VIP) supports the functional simulation of Versal adaptive SoC applications.
The Versal™ adaptive compute acceleration platforms Control, Interfaces, and Processing System (CIPS) Verification Intellectual Property (VIP) supports the functional simulation of Versal adaptive SoC applications. It is targeted to enable the functional verification of programmable logic (PL) by mimicking the processor system (PS)-PL interfaces and OCM memories of PS logic. This VIP is delivered as a package of System Verilog® modules. VIP operation is controlled by using a sequence of System Verilog tasks.
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