ISE Release Notes
This document contains a listing of release note tables, one for each IP core.
by: AMD
With this core, the AMD Universal Serial Bus 2.0 High Speed Device provides a control interface to internal registers via a 32-bit Processor Local Bus (PLB) Version 4.6 as described in the IBM® CoreConnect™ 128-Bit Processor Local Bus, Architectural Specification Version 4.6.
With this core, the AMD Universal Serial Bus 2.0 High Speed Device provides a control interface to internal registers via a 32-bit Processor Local Bus (PLB) Version 4.6 as described in the IBM® CoreConnect™ 128-Bit Processor Local Bus, Architectural Specification Version 4.6.
This PLB slave interface supports single beat read and write data transfers (no burst transfers). This interface is suitable for USB-centric,high-performance designs, bridges and legacy port replacement operations.
LogiCORE™ | Version | Interface Support | Software Support | Supported Device Families |
---|---|---|---|---|
XPS USB 2.0 Device | v7.01a | AXI4 | EDK™ 14.3 | Virtex™ 6 Virtex 5 LXT / SXT / LX Virtex 4 FX / LX / SX Spartan™ 6 LX / LXT Spartan 3 / 3 XA Spartan 3A / 3AN / 3A DSP Spartan 3E / 3E XA |
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.