Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
作者: AMD
The AMD LogiCORE™ 25G IEEE 802.3by RS-FEC IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) sublayer.
AMD offers the 25 Gigabit IEEE 802.3by Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise applications. This core is designed to the IEEE 802.3by and 25G Ethernet Consortium Schedule 3 specification and connects seamlessly to the AMD soft 25G Ethernet Subsystem IP on Virtex™ UltraScale™, Virtex UltraScale+™, Kintex™ UltraScale+, and Zynq™ UltraScale+ devices.
Hardware Evaluation Time Out Period * : ~ 8 hrs
| LogiCORE™ | Version | AXI Support | Software Support | Supported Device Families | 
|---|---|---|---|---|
| 25G IEEE 802.3by Reed-Solomon Forward Error Correction | v1.0 | AXI4-Lite | Vivado™ 2016.1 | Kintex™ UltraScale+™ Virtex™ UltraScale+ Zynq™ UltraScale+ Virtex UltraScale™  | 
Download the required software from the AMD Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.