作者: AMD
The Chroma Resampler IP Core enables convenient conversion between supported video formats.
Obsoleted in 2019.1 and not recommended for new designs.
Relacement is the LogiCORE™, Video Processing Subsystem which is a license free IP and bundled with Vivado™.
Please refer to Product Discontinuation Notice XCN18017.
The Chroma Resampler LogiCORE IP converts video data between commonly used chroma formats.
The Chroma Resampler core converts between chroma formats of 4:4:4, 4:2:2, and 4:2:0. There are six conversions available for the three supported formats. Conversion is achieved using a FIR filter approach. Some conversions require filtering in only the horizontal dimension, vertical dimension, or both. Interpolation operations are implemented using a two-phase polyphase FIR filter. Decimation operations are implemented using a low-pass FIR filter to suppress chroma aliasing.
Obsoleted in 2019.1 and not recommended for new designs.
Relacement is the LogiCORE™, Video Processing Subsystem which is a license free IP and bundled with Vivado™.
Please refer to Product Discontinuation Notice XCN18017.
| LogiCORE™ | Version | AXI4 Support | Software Support | Supported Device Families |
|---|---|---|---|---|
| Chroma Resampler Discontinued |
v4.0 | AXI4-Stream AXI4-Lite |
Vivado™ 2015.4 | Kintex™ UltraScale+™ Virtex™ UltraScale+ Zynq™ UltraScale+ Kintex UltraScale™ Virtex UltraScale Zynq 7000 Artix™ 7 Kintex 7 Virtex 7 |
| Chroma Resampler |
v3.01a | AXI4-Stream AXI4-Lite |
ISE™ 14.3 | Zynq 7000 Artix 7 Kintex 7 Virtex 7 Virtex 6 CXT / HXT / LXT / SXT Spartan™ 6 LXT / LX |
Download the required software from the AMD Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.
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