by: AMD
Viterbi Decoders are used in systems where data are transmitted and subject to errors before reception.
Viterbi Decoders are used in systems where data are transmitted and subject to errors before reception. Compatible with many common standards such as DVB, 3GPP2, IEEE802.16, HiperLAN, Intelsat IESS-308/309, the Viterbi Decoder LogiCORE™ IP, along with other forward error correction cores from AMD offers highly-flexible concatenated codecs. The Viterbi Decoder LogiCORE IP consists of two basic architectures: a fully parallel implementation which gives fast data throughput and a serial implementation which occupies a small area. The core also has a puncturing option, giving a large range of transmission rates and reducing the bandwidth requirement on the channel. Puncturing can also be carried out externally to the decoder and the erasure pins in the erasure bus ERASE can be asserted to indicate the presence of null-symbols.
Hardware Evaluation Time Out Period * : ~ 2-3 hrs
| LogiCORE™ | Version | AXI Support | Software Support | Supported Device Families |
|---|---|---|---|---|
| Viterbi Decoder | v9.1 | AXI4-Stream | Vivado™ 2021.1 | Kintex™ UltraScale+™ Virtex™ UltraScale+ Zynq™ UltraScale+ Kintex UltraScale™ Versal™ adaptive SoC Virtex UltraScale Zynq 7000 Artix™ 7 Kintex 7 / 2L Virtex 7 / XT / HT |
| Viterbi Decoder | v8.0 | AXI4-Stream | ISE™ 14.4 | Artix 7 Kintex 7 / 2L Virtex 7 / 2L / XT Virtex 6 CXT / HXT / LXT / SXT Spartan™ 6 LX / LXT |
| Viterbi Decoder | v7.0 | Legacy | ISE 14.1 | Artix 7 Kintex 7 / 2L Virtex 7 / 2L / XT Virtex 6 CXT / HXT / LXT / SXT Virtex-5 FXT / SXT / LXT Virtex-5 LX Virtex 4 FX / SX / LX Spartan 6 LX / LXT Spartan 3A DSP Spartan 3 |
Download the required software from the AMD Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.