作者: AMD
The LogiCORE™ IP SDI Tx and RX Video Bridge cores are designed to interface the SDI ports of the SMPTE SDI core to the video ports of the AXI4-Stream core.
The core is removed from IP catalog as of 2014.2. Users who need a bridge from SDI to AXI can request an unsupported copy of the source code for the SDI Bridges from the following Secure site.
The LogiCORE™ IP SDI Tx and RX Video Bridge cores are designed to interface the SDI ports of the SMPTE SDI core to the video ports of the AXI4-Stream core. The input of the SDI Rx Video Bridge is an SDI virtual interface that has one to four 10-bit data streams with embedded synchronization. The output is video data with explicit synchronization signals. This core extracts synchronization signals, reformats the video data, and provides clock enables. The input of the SDI TX Video Bridge core is Video data with explicit synchronization signals. The output is an SDI virtual interface with one to four 10-bit data streams and embedded synchronization.
| LogiCORE™ | Version | Software Support | Supported Device Families |
|---|---|---|---|
| SDI to Video Bridges | v1.0 | Vivado™ 2013.3 | Zynq™ 7000 Artix™ 7 Kintex™ 7 Virtex™ 7 |
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