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Video In to AXI4-Stream

作者: AMD

The Video In to AXI-4 Stream LogiCORE™ IP core converts common parallel video signals (such as from a DVI PHY) to an AXI4-Stream interface.

设计工具支持: Vivado Software, ISE Design Suite
捆绑产品: Vivado Software, ISE Design Suite
授權: End User License Agreement
器件支持: Artix 7, Kintex 7, Kintex UltraScale, Kintex UltraScale+, Virtex 7, Virtex UltraScale, Virtex UltraScale+, Versal AI Core, Zynq 7000, Zynq UltraScale+ MPSoC

Overview
Documentation
Supported Tool Versions

Product Description

Included at no additional charge with Vivado™ software.

AMD Video in to AXI4-Stream IP core enables video designers to quickly and easily connect external video signals to video processing blocks that use AXI4-Stream.

The Video In to AXI-4 Stream LogiCORE™ IP core converts common parallel video signals (such as from a DVI PHY) to an AXI4-Stream interface. The input video signals must have data, clock, DE, sync signals (Vsync and Hsync) and/or blanking signals (Vblank and Hblank). The AXI4-Stream interface signals are compliant to the AXI4-Stream Video Protocol as defined in the AXI Reference Guide (UG761), and as is implemented on most AMD Video IP cores. This enables video designers to quickly and easily connect an external video source to subsequent processing blocks that use a video protocol on the AXI4-Stream interface (such as AMD Video IP). This core works in conjunction with the AMD Video Timing Controller (VTC) core to detect characteristics of the incoming video format that can be read by a system processor and used to configure subsequent processing blocks. Source code is provided with the core to allow customers to adapt the core to work with unique video signals that may not already be included in the core.

Key Features and Benefits

Configurable input data width accepts 8-64 bits enabling use with a variety of video source types and video data formats such as DVI, sub-sampled image sensor data, monochrome data, etc.
AXI4-Stream interface is compliant with the AXI4-Stream Video Protocol as described in the AXI Reference Guide (UG761)
Supports 1080P60 pixel clock rates in all supported devices families
Supports 4kx2k at 24Hz clock rates in supported high performance devices
Designed to operate in conjunction with the AMD Video Timing Controller IP Core
Handles asynchronous clock boundary crossing between video clock domain and AXI4-Stream clock domain

Resource Utilization

Video In to AXI4-Stream Resource Utilization

Documentation

Vivado Release Notes

The most updated Release Note.

View Release Note

Download Video In to AXI4-Stream Test Bench

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FPGA Video Design Hub (DH235)

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