作者: AMD
The XDMA/QDMA Simulation IP core is a SystemC-based abstract simulation model for XDMA/QDMA and enables the emulation of Xilinx Runtime (XRT) to device communication.
The XDMA/QDMA Simulation IP core is a SystemC-based abstract simulation model for XDMA/QDMA and enables the emulation of Xilinx Runtime (XRT) to device communication. With this IP a Xilinx Runtime host application (through OpenCL™ APIs) can communicate with kernels,memories, and streaming resources, but the communication is at the transaction level and does not model PCIe®-level communication as in actual hardware.
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