Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
作者: AMD
The Universal Serial 10GE Media Independent Interface (USXGMII) IP core implements an Ethernet Media Access Controller (MAC) with a mechanism to carry a single port of 10M, 100M, 1G, 2.5G, 5G or 10GE over an IEEE 802.3 Clause 49 BASE-R physical coding sublayer/physical layer (PCS/PHY).
The Universal Serial 10GE Media Independent Interface (USXGMII) IP core implements an Ethernet Media Access Controller (MAC) with a mechanism to carry a single port of 10M, 100M, 1G, 2.5G, 5G or 10GE over an IEEE 802.3 Clause 49 BASE-R physical coding sublayer/physical layer (PCS/PHY). The USXGMII IP core is delivered as encrypted register transfer level (RTL) through the Vivado™ Design Suite targeted for UltraScale+™ and UltraScale™ devices.
Full access to this IP core, including bitstream generation capability, requires that you generate and install a Full License Key.
Please refer to the Requirements link on the product page for this core for information on:
This core is licensed under the following terms: Core License Agreement.
To purchase a LogiCORE™ IP core, contact your local Sales Representative referencing the part number in the table below:
| LogiCORE Product Name | Part Number |
| USXGMII Subsystem | EF-DI-USXGMII-MAC-SITE |
After purchasing a license for this core, follow the instructions in the purchase confirmation email you will receive on downloading the IP core netlist from the Licensing Site, and on generating and installing a Full license key to activate Full access to the core.
For information on New Features, Known Issues, and Patches please refer to the Installation, Licensing and release Notes document available on the Licensing Solution Center.
Hardware Evaluation Time Out Period * : ~ 8 hrs
| LogiCORE™ | Version | Support | Software Support | Supported Device Families |
|---|---|---|---|---|
| USXGMII Subsystem EF-DI-USXGMII-MAC-SITE |
v1.2 | AXI4-Stream 32-bit Optional AXI4-Lite |
Vivado™ 2022.1 | Versal™ Adaptive SoC Artix™ UltraScale+™ Kintex™ UltraScale+ Virtex™ UltraScale+ Zynq™ UltraScale+ MPSoC Kintex UltraScale™ Virtex UltraScale Versal 7 |
Download the required software from the AMD Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.