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Adder/Subtracter

作者: AMD

The Adder/Subtracter IP provides LUT and single DSP slice add/sub implementations.

设计工具支持: Vivado Software, ISE Design Suite
捆绑产品: Vivado Software, ISE Design Suite
授權: End User License Agreement
器件支持: Artix 7, Kintex 7, Kintex UltraScale, Kintex UltraScale+, Spartan 7, Spartan UltraScale+, Versal AI Core, Versal AI Edge, Versal HBM, Versal Premium, Versal Prime, Virtex 6, Virtex 7, Virtex UltraScale, Virtex UltraScale+, Zynq 7000, Zynq UltraScale+ MPSoC

Overview
Documentation
Supported Tool Versions

Product Description

The Adder/Subtracter IP provides LUT and single DSP slice add/sub implementations. The Adder/Subtracter module can implement adders (A+B), subtracters (A–B), and dynamically configurable adder/subtracters which operate on signed or unsigned data. The function can be implemented in a single DSP slice or LUTs. The module can be pipelined.

Key Features and Benefits

Generates adder, subtracter and add/subtracter functions
Supports two’s complement-signed and unsigned operations
Supports fabric implementation inputs ranging from 1 to 256 bits wide
Supports DSP slice implementations with inputs up to 58 bit
Optional carry input and output.
Optional clock enable and synchronous clear
Optional bypass (load) capability
Option to set the B Value to a constant
Optional pipelined operation
For use with AMD Vivado™ IP Catalog, AccelDSP™ Synthesis Tool, System Generator, and Vitis™ Model Composer

Resource Utilization

Adder/Subtracter Resource Utilization

Documentation

Vivado IP Release Notes

This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.

View Release Note

DS214 - LogiCORE IP Adder/Subtracter v11.0 Data Sheet (DS214) (v11.0)

The AMD LogiCORE™ IP Adder/Subtracter core provides LUT and single XtremeDSP™ slice add/sub implementations. The Adder/Subtracter module can create adders (A+B), subtracters (A–B), and dynamically configurable adder/subtracters which operate on signed or unsigned data.

View Data Sheet

PG120 - Adder/Subtracter v12.0 Product Guide (PG120) (v12.0)

Adder/Subtracter core provides LUT and single XtremeDSP slice add/sub implementations.

View Product Guide