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RAM-based Shift Register

作者: AMD

設計工具支援: Vivado Software
隨附於: Vivado Software, ISE Design Suite
授權: End User License Agreement
器件支援: Kintex 7, Kintex UltraScale, Kintex UltraScale+, Virtex 6, Virtex 7, Virtex UltraScale, Virtex UltraScale+, Versal AI Core, Versal Prime, Zynq 7000, Zynq UltraScale+ MPSoC, Spartan 6, Artix 7

Overview
Documentation
Supported Tool Versions

Product Description

The AMD LogiCORE™ RAM-based Shift Register IP core generates fast, compact FIFO-like-style registers, delay lines or time-skew buffers using the SRL16/SRL32 mode of the slice LUTs available in AMD FPGA devices. Implementing Shift Registers with the SRL16/SRL32 provides large resource and power savings. The IP supports fixed-length or variable-length shift registers.

Key Features and Benefits

Generates fast, compact, FIFO-style shift registers or delay lines using the SRL16/SRL32 mode of the slice LUTs
User options to create fixed-length or variable-length shift registers
Speed or resource optimization for variable length shift registers
Optional output register with clock enable and synchronous controls for variable length shift registers

Resource Utilization

RAM-based Shift Register Resource Utilization

Documentation

Vivado Release Notes

The most updated Release Note.

View Release Note

DS228 - LogiCORE IP RAM-based Shift Register v11.0 Data Sheet (DS228) (v11.1)

The AMD LogiCORE™ IP RAM-based Shift Register core provides a very efficient multi-bit wide shift register for use in FIFO-like applications or as a delay line. Fixed-length shift registers and variable-length shift registers can be created.

View Data Sheet

PG122 - RAM-Based Shift Register v12.0 Product Guide (PG122) (v12.0)

The RAM-based Shift Register core provides a very efficient multi-bit wide shift register for use in FIFO-like applications or as a delay line. Fixed-length shift registers and variable-length shift registers can be created.

View Product Guide