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    AMD Intellectual Property

RAM-based Shift Register

作者: AMD

The AMD LogiCORE™ RAM-based Shift Register IP core generates fast, compact FIFO-like-style registers, delay lines or time-skew buffers using the SRL16/SRL32 mode of the slice LUTs available in AMD FPGA devices.

  • 设计工具支持: Vivado Software
  • 捆绑产品: Vivado Software, ISE Design Suite
  • 授權: End User License Agreement
  • 器件支持: Kintex 7, Kintex UltraScale, Kintex UltraScale+, Virtex 6, Virtex 7, Virtex UltraScale, Virtex UltraScale+, Versal AI Core, Versal Prime, Zynq 7000, Zynq UltraScale+ MPSoC, Spartan 6, Artix 7