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Multiply Accumulator

作者: AMD

The Multiply Accumulator IP accepts two operands, a multiplier and a multiplicand, and produces a product (A*B=Prod) that is added/subtracted to the previous adder/subtracter result (S=S+/-Prod).

設計工具支援: Vivado Software, ISE Design Suite
隨附於: ISE Design Suite
授權: End User License Agreement
器件支援: Artix 7, Kintex 7, Virtex 6, Virtex 7, Spartan 6, Spartan 3, Spartan 3A, Spartan 3A DSP, Spartan 3E, Virtex 4, Virtex 5

Overview
Documentation
Supported Tool Versions

Product Description

Obsoleted in 2014.1 and not recommended for new designs.

Functionality can be implemented using RTL inference directly.

The Multiply Accumulator IP accepts two operands, a multiplier and a multiplicand, and produces a product (A*B=Prod) that is added/subtracted to the previous adder/subtracter result (S=S+/-Prod). This product value can be loaded with assertion of Bypass (S=Prod). The Multiply Adder IP is implemented using Xtreme DSP™ slices and operates on signed or unsigned data.

Key Features and Benefits

Supports multiplier inputs ranging from 1 to 31 bits unsigned or 2 to 32 bits signed and an output width ranging from 1 to 79 bits unsigned or 2 to 80 bits signed
Latency can be set for optimal speed or the minimal amount of pipelining allowed "Latency = 1" (accumulation register required)
Instantaneous Resource Estimation
For use with AMD CORE Generator™

Documentation

Vivado Release Notes

The most updated Release Note.

View Release Note