作者: AMD
The PLBv46 Endpoint is an interface between the Processor Local Bus (PLB) and the PCI Express® (PCIe®) silicon hard core.
The PLBv46 Endpoint is an interface between the Processor Local Bus (PLB) and the PCI Express® (PCIe®) silicon hard core. The PLBv46 Endpoint sub-system provides full bridge functionality between the PLB bus architecture and the PCIe network. The sub-system is composed of the PCIe core, one GT interface and the PLBv46 Endpoint. The bridge circuit is implemented in the FPGA fabric and the PCIe core and GT are hard-core elements in the FPGA.
The PLBv46 Endpoint provides a transaction level translation of PLB bus commands to PCIe TLP packets and PCIe requests to PLB bus commands.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.