UG973 - Vivado Release Notes
Vivado Design Suite User Guide: Release Notes, Installation, and Licensing.
作成者: AMD
The AXI Switch IP connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.
The AXI Switch IP connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI Switch is a RTL-based IP with manual user configuration. Once customized, the generated component wrapper is intended to be instantiated into a RTL design. The AXI Switch can also be included in RTL modules to be packaged into custom IP.
LogiCORE™ | Version | AXI4 Support | Software Support | Device Families |
AXI Switch | V1.0 | AXI4 AXI4-Lite AXI3 |
Vivado™ 2025.1 | Versal™ Adaptive SoC Artix™ 7 Kintex™ 7 Kintex UltraScale™ Kintex UltraScale+™ Virtex™ 7 Virtex UltraScale Virtex UltraScale+ Zynq™ UltraScale+ MPSoC |
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