作者: AMD
The LogiCORE™ RapidIO Logical (I/O) and Transport Layer Interface is optimized for Virtex™ II and Virtex II Pro series FPGAs and is compliant with Logical Input/Output and Common Transport Specification 1.2.
LogiCORE™ IP Serial RapidIO v5.6 – SRIO Gen 1.3 (with extensions for Gen 2 -5G line rate) Support.
For the Serial RapidIO Gen 2 LogiCORE IP, please click here.
The LogiCORE IP Serial RapidIO Endpoint solution, designed to RapidIO Gen 1.3 specification with Gen 2 -5G line rate support, comprises of a highly flexible and optimized Serial RapidIO Physical Layer core and a Logical (I/O) AND Transport Layer core. This core is designed to ensure predictable timing, thereby significantly reducing engineering time investment and allowing resources to be focused on user-specific application logic.
The RapidIO Logical (I/O) and Transport Layer core and the RapidIO Physical Layer core, provide a complete Serial RapidIO protocol stack. Additionally, a highly optimized and configurable buffer design is included with these cores to implement a Serial RapidIO endpoint. While a modular IP design approach provides flexibility to enable ease of customization, the AMD tool chain automates generation of the serial endpoint on an FPGA by using these building block IP cores through a configurable and easy-to-use graphical user interface.
Hardware Evaluation Time Out Period * : ~ 8 hrs
| LogiCORE™ | Version | Software Support | Supported Device Families |
|---|---|---|---|
| RapidIO Physical Layer Interface Core Gen 1 | v5.6 | ISE™ 13.1 | Virtex™ 6 HXT / LXT / SXT Virtex 5 FXT / SXT / LXT Virtex 4 FX Spartan™ 6 LXT |
Download the required software from the AMD Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.