Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
von: AMD
The AMD 200G/400G High Speed Ethernet (200G/400G HSEC) Subsystem provides the 200G or 400G Ethernet Media Access Control (MAC) with a Physical Coding Sublayer (PCS) including Reed-Solomon Forward Error Correction (RS-FEC) or a standalone 200G or 400GAUI-16 PCS/PMA with RS-FEC.
The AMD 200G/400G High Speed Ethernet (200G/400G HSEC) Subsystem provides the 200G or 400G Ethernet Media Access Control (MAC) with a Physical Coding Sublayer (PCS) including Reed-Solomon Forward Error Correction (RS-FEC) or a standalone 200G or 400GAUI-16 PCS/PMA with RS-FEC.
The 200G/400G Ethernet Subsystem is designed to the IEEE 802.3bs standard. Increased demand from mobile traffic and cloud computing is forcing next generation routers and switches to 400G and beyond.
The AMD 200G/400G Ethernet Subsystem is provided in netlist form to licensed Ethernet customers only. The netlist is configured based upon user provided details. As described in the ordering information below, a confirmation email which includes configuration details will be sent to you.
The sole purpose of the Ethernet cores is to help you develop designs for AMD devices. AMD reserves the right to deny access to the Ethernet core products. The Ethernet cores are licensed under the Core License Agreement.
To purchase any of these IP cores, contact your local Sales Representative referencing the appropriate part number(s) in below table.
| Product Name | Part Number |
| 200G Ethernet MAC + 200GAUI | EM-DI-200GEMAC-PROJ |
| 200GAUI | EM-DI-200GAUI-PROJ |
| 400G Ethernet MAC + 400GAUI |
EM-DI-400GEMAC-PROJ |
| 400GAUI | EM-DI-400GAUI-PROJ |
As part of the notification for the Ethernet configuration, you will be asked to accept the Core Project License Agreement. The email address associated with your AMD.com account must be a valid company email address in order for the netlist to be approved.
Once you have executed the Core License Agreement and the core has been configured to specification, the LogiCORE™ IP for AMD FPGAs will be provided to you.
Hardware Evaluation Time Out Period * : ~ 8 hrs
| LogiCORE™ | Version | Software Support | Supported Device Families |
|---|---|---|---|
| 200G/400G Ethernet Subsystem |
v2.1 | Vivado™ 2020.1 | Virtex™ 7 UltraScale+™ |
Download the required software from the AMD Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.