Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
von: AMD
The LogiCORE™ 32G Fibre Channel (32GFC) RS-FEC IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) sublayer as described in the INCITS Fibre Channel Framing and Signaling T11/15-253v2 specification.
The LogiCORE™ 32G Fibre Channel (32GFC) RS-FEC IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) sublayer as described in the INCITS Fibre Channel Framing and Signaling T11/15-253v2 specification.
Hardware Evaluation Time Out Period * : ~ 2-3 hrs
LogiCORE™ | Version | Software Support | Supported Device Families |
---|---|---|---|
Fibre Channel 32GFC Reed-Solomon Forward Error Correction | v1.0 | Vivado™ 2022.1 | Versal™ Premium Kintex™ UltraScale+™ Virtex™ UltraScale+ Zynq™ UltraScale+ Virtex UltraScale™ |
Download the required software from the AMD Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.