Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
作成者: AMD
The AXI High Bandwidth Internal Configuration Access Port (HBICAP) LogiCORE™ IP core for the AXI Interface enables an embedded microprocessor, such as the MicroBlaze™ processor, to read and write the FPGA configuration memory through the internal configuration access port (ICAPEn).
The AXI High Bandwidth Internal Configuration Access Port (HBICAP) LogiCORE™ IP core for the AXI Interface enables an embedded microprocessor, such as the MicroBlaze™ processor, to read and write the FPGA configuration memory through the internal configuration access port (ICAPEn). This enables you to write software programs that modify the circuit structure and functionality during the operation of the circuit.
Note: The ICAPE2 primitive is applicable for 7 series devices. The ICAPE3 primitive is applicable forUltraScale™ and UltraScale+™ devices.
LogiCORE™ | Version | AXI4 Support | Software Support | Supported Device Families |
---|---|---|---|---|
AXI Hardware ICAP | v1.0 | AXI4-Lite AXI4-Stream AXI4-MM |
Vivado™ 2019.2 | Kintex™ 7 UltraScale+™ Virtex™ 7 UltraScale+ Zynq™ 7000 UltraScale+ Kintex 7 UltraScale™ Virtex 7 UltraScale Artix™ 7 Kintex 7 Virtex 7 Zynq 7000 |
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