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AXI Memory Mapped to PCI Express® (PCIe®) Gen2

作成者: AMD

The AXI Memory Mapped to PCIe® Gen2 IP is designed for the AMD Embedded Development Kit (EDK™) and AMD Platform Studio tool flow.

デザインツールサポート: Vivado Software, ISE Design Suite
バンドル内容: Vivado Software, Embedded Development Kit
ライセンス: End User License Agreement
デバイスサポート: Artix 7, Kintex 7, Virtex 7, Zynq 7000

Overview
Documentation
Supported Tool Versions

Product Description

The AXI Memory Mapped to PCIe® Gen2 IP core provides an interface between the AXI4 interface and the Gen2 PCI Express® (PCIe) silicon hard core. The AXI4 PCIe provides full bridge functionality between the AXI4 architecture and the PCIe network. The IP is composed of the PCIe core, the GT interface and the AXI4 interface. The bridge circuit is implemented in the FPGA fabric and the PCIe core and GT are integrated elements in the FPGA.

The AXI4 PCIe core provides a transaction level translation of AXI4 commands to PCIe TOP packets and the PCIe requests to AXI4 commands.

Key Features and Benefits

Support AXI4 memory access to PCIe memory
Provide AXI4 master access for PCIe devices
Translate AXI4 transactions to appropriate PCIe Transaction Layer Packets (TLP) packets
Track and Manage PCIe TLPs that require completion processing
Indicate error conditions detected by the PCIe core through interrupt

Resource Utilization

AXI Memory Mapped To PCI Express

Documentation

Vivado IP Release Notes

This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.

View Release Note

DS820 - LogiCORE IP AXI RC/EP Bridge for PCI Express (v1.03.a) Data Sheet (AXI) (DS820) (v1.03a)

The Advanced eXtensible Interface (AXI) Root Port/Endpoint (RP/EP) Bridge for PCI Express® is an interface between the AXI4 and PCI Express. Definitions and references are provided in this document for all of the functional modules, registers, and interfaces that are implemented in the AXI Bridge for PCI Express. This document contains information about the AXI4 version of the core.

View Data Sheet