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UltraScale+™ GTM Transceivers Wizard

作成者: AMD

The UltraScale+™ GTM Wizard core is used to configure and simplify the use of one or more GTM serial transceivers in a AMD UltraScale+ device.

デザインツールサポート: Vivado Software
バンドル内容: Vivado Software
ライセンス: End User License Agreement
デバイスサポート: Virtex UltraScale+

Overview
Documentation
Supported Tool Version

Product Description

The UltraScale+™ FPGAs GTM Tranceivers Wizard IP core helps configure one or more serial transceivers. You can start from scratch, input your requirements, and generate valid configurations. The flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you have selected, optionally including a variety of helper blocks to simplify common functionality. In addition, the Wizard can produce an example design for simple simulation and hardware usage demonstration.

Key Features and Benefits

Simple and intuitive feature selection flow
Automatically sets transceiver parameters
Available helper blocks to simplify common or complex transceiver usage
Example design with configurable PRBS generator, checker, and link status indicator to demonstrate functionality in simulation and hardware
Support for UltraScale+ GTM architectures.
Customization flow driven by the Vivado Integrated Design Environment (IDE), providing highlevel choices that configure supported transceiver features and automatically set primitive parameters, as appropriate
Advanced configuration options to tune transceiver performance
Available helper blocks to simplify common or complex transceiver usage, and the choice to either include or exclude each helper block from the core
- Helper blocks excluded from the core are delivered as user-customizable starting points within the example design
Synthesizable example design with configurable pseudo-random binary sequence (PRBS) data generator, checker, and link status indicator logic to quickly demonstrate core and transceiver functionality in simulation
- Simulation test bench that monitors example design PRBS lock in external loopback, and indicates resulting link status
- Additional convenience features, including differential reference clock buffer instantiation and wiring, and dual vector slicing