作成者: AMD
SmartConnect Network-on-Chip (SC_NoC) enables systematic packet-based data movement for long reach on FPGAs.
SmartConnect Network-on-Chip (SC_NoC) enables systematic packet-based data movement for long reach on FPGAs. This new IP implements a soft NoC for Vivado™ users building custom applications that require AXI interconnect at client interfaces.
This product also includes a NoC Memory Subsystem IP for Vitis™ users targeting Alveo™ platforms. This memory subsystem IP enables efficient multi-DDR access with SC_NoC, increasing addressable memory available to compute applications.
In addition to standard SmartConnect features, SmartConnect NoC has the following characteristics:
NoC Memory Subsystem provides the following benefits:
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