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200G IEEE 802.3bs Reed Solomon Forward Error Correction

von: AMD

The LogiCORE™ 200G IEEE 802.3bs Reed Solomon Forward Error Correction IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) functions within the Physical Coding Sublayer.

Part Number:
- EF-DI-200G-RS-FEC-PROJ
- EF-DI-200G-RS-FEC-SITE
Design Tools Support: Vivado Software
Lizenz: Core License Agreement
Device Support: Kintex UltraScale+, Virtex UltraScale+, Versal AI Core, Versal Prime

Overview
Documentation
Supported Tool Version

Product Description

The LogiCORE™ 200G IEEE 802.3bs Reed Solomon Forward Error Correction IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) functions within the Physical Coding Sublayer.

Key Features and Benefits

IEEE Std. 802.3-2018 TX and RX
Support for 200G Ethernet FEC
- Option to use Virtex™ UltraScale+™ GTM transceivers for significant resource reduction
- Low latency soft IP implementation
Dynamic latency reporting
Configuration and status bus
Supports RS (544,514) KP4 encode and decode
Supports symbol error statistics (including per-lane statistics)

Resource Utilization

200G IEEE 802.3bs Reed Solomon Forward Error Correction Resource Utilization (Registration Required)

Documentation

Vivado IP Release Notes

This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.

View Release Note