作成者: AMD
RAMA IP, made available for Virtex™ UltraScale+™ HBM devices, attaches between an AXI fabric master and the HBM AXI slave infrastructure.
Thread Synthesis and Reordering attachment IP for use with random access masters to HBM IP.
For use with single-threaded, random access masters to improve overall HBM bandwidth.
RAMA IP, made available for Virtex™ UltraScale+™ HBM devices, attaches between an AXI fabric master and the HBM AXI slave infrastructure. It generates temporary IDs so that transactions with the same original ID may be reordered. This relieves congestion within the HBM switch and allows transactions to complete based on the native latency of the memory. Data is then coalesced within RAMA and returned in the order it was requested.
Included at no additional charge with Vivado™ software
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.