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UltraScale™ Gen3 Integrated Block for PCI Express® (PCIe®)

作成者: AMD

AMD provides a PCI Express® Gen3 Integarated block for PCI Express (PCIe®) in the UltraScale™ family of FPGAs.

デザインツールサポート: Vivado Software
バンドル内容: Vivado Software
ライセンス: End User License Agreement
デバイスサポート: Kintex UltraScale, Virtex UltraScale

Overview
Documentation
Supported Tool Version

Product Description

AMD provides a PCI Express® Gen3 Integrated block for PCI Express (PCIe®) in the UltraScale™ family of FPGAs. The UltraScale™ FPGA solution for PCI Express Gen3 includes all of the necessary components to create a complete solution for PCIe. Delivered through Vivado™, the AMD IP for Endpoint and Root Port simplifies the design process and reduces time-to-market.

Recommended for:

High Peformance and High Bandwidth Applications
Compute and Data Co-processing Applications
Medical Imaging, High-Performance Computing & Communications Packet Processing

Deliver:

The AMD Integrated Block for PCIe is provided at no additional cost

Key Features and Benefits

Compliant with the PCI Express Base Specification 3.0
Supported Lane width: x1, x2, x4 and x8
Fully compliant with PCI Express transaction ordering rules
Optimal buffering for high bandwidth Direct Memory Access (DMA) applications
Bandwidth scalability interconnect width
AXI4-Stream Interface

Resource Utilization

UltraScale™ FPGA Gen3 Integrated Block for PCI Express Resource Utilization

Documentation

Vivado Release Notes

The most updated Release Note.

View Release Note

PG156 - UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156) (v4.4)

Describes the UltraScale™ Architecture Gen3 Integrated Block for PCI Express® core, which is a reliable, high-bandwidth, scalable serial interconnect building block.

View Product Guide

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v4.3 Product Guide (PG023) (v4.3)

This application note describes the use of a bridge from the Completer Streaming Interfaces of the Gen3 Integrated Block for PCI Express IP core to an AXI4-Lite master interface.

View Application Note xapp1201.zip