View release highlights for previous versions of AMD Vivado™ here.

AMD Vivado™ Design Suite 2026.1 Software Release Highlights:

New subscription-based licensing model with more flexible licensing options

NoC and QoR enhancements for AMD Versal™ ​devices

  • Multi-top NoC simulation, new text-based report and logical NoC viewer
  • QoR enhancements with retiming updates, XPM memory optimization, and mixed RAM directive

DFX + Segmented Configuration support within PL

  •  Enabling the Dynamic Function eXchange (DFX) flow within the programmable logic for 2nd generation Versal devices with Segmented Configuration as the default flow​

Advanced Configuration Editor (ACE)

  • A stand-alone, design-aware utility that helps define and manage the subsystem composed of processors, memory, and peripherals
  • Applies safety and security requirements to the subsystem

Ease-of-Use Enhancements

  • Enhanced HDL support​
  • Processing System Wizard improvements
  • GUI improvements​

AMD Vivado™ Design Suite 2026.1 What's New by Category

Expand the sections below to learn more about the new features and enhancements in Vivado 2026.1.

New devices supported:

  • AMD Versal™ AI Edge Series Gen 2: XC2VE3358, XC2VE3504, XC2VE3558, XC2VE3804, and XC2VE3858 with new packages and speed grades
  • AMD Versal Prime Series Gen 2: XC2VM3558 and XC2VM3858 with new packages and speed grades
  • AMD Versal RF: XCVR1602 and XCVR1652
  • AMD Spartan™ UltraScale+™: XCSU45P, XCSU60P and XCSU200P

  • Multi-top NoC simulation: New parallel top-level instance automatically created for NoC simulation, allowing a cleaner solution that does not disrupt the user’s top-level simulation structure
  • New text-based NoC report: A unified report for all NoC elements in the design to better understand QoS requirements ​
  • Logical NoC viewer: A new and separate graphical viewer that displays all NoC masters (NMUs) and NoC slaves (NSUs), including the virtual NoC interfaces / INI instances, across the entire design

  • Versal QoR enhancements with retiming updates, XPM memory optimization, and mixed RAM directive

  • A stand-alone, design-aware utility that helps define and manage the subsystem composed of processors, memory, and peripherals
  • Applies safety and security requirements to the subsystem

  • Processing System Wizard improvements for Versal devices
    • Support for MIO voltage configuration per I/O bank and cluster-aware power analysis
    • Support for security and device integrity features through the Processing System Wizard
    • Ability to update the PLM without requiring a full system reboot
    • Addition of interactive block diagram support for Versal RF devices

  • Enabling the Dynamic Function eXchange (DFX) flow within the programmable logic for 2nd generation Versal devices with Segmented Configuration as the default flow
  • Updated lock_design level routing command to lock the static portion of the DFX design after implementation from initial configuration 

  • Enhanced HDL support with new constructs from VHDL 2008 and VHDL 2019 are supported in synthesis as well as simulation
  • New look and feel for Vivado IDE, making the interface more intuitive and visually appealing
  • Board-infrastructure-based filtering to view the list of example designs