作成者: AMD
The Multiply Adder IP performs a multiplication of two operands and adds (or subtracts) the full-precision product to a third operand.
The Multiply Adder IP performs a multiplication of two operands and adds (or subtracts) the full-precision product to a third operand. The Multiply Adder IP is implemented using DSP slices and operates on signed or unsigned data.
| LogiCORE™ | Version | Software Support | Supported Device Families |
|---|---|---|---|
| Multiply Adder | v3.0 | Vivado™ 2014.2 | Kintex™ UltraScale™ Virtex™ UltraScale Zynq™ 7000 Artix™ 7 Kintex 7 / 2L Virtex 7 / 2L / XT |
| Multiply Adder | v2.0 | ISE™ 14.1 | Artix 7 Kintex 7 / 2L Virtex 7 / 2L / XT Virtex 6 CXT / HXT / SXT / LXT/ -1L Virtex 5 TXT / SXT / LXT / FXT Virtex 4 SX / LX / FX Spartan™ 6 LX / LXT Spartan 3A DSP |
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