作成者: AMD
Output DDR Flip Flop allows designers to avoid additional timing complexities and CLB usage.
This design element is a dedicated output register for use in transmitting double data rate (DDR) signals from FPGA devices. This primitive is typically used to drive a clock signal out of the FPGA. This feature allows designers to avoid additional timing complexities and CLB usage. The ODDR also works with SelectIO™ features. For more details refer to SelectIO™ Wizard documentation.
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