AMD Adaptive SoC and FPGA device files that support PCB design, validation and manufacturing test.
- Package Pinout Files
- BSDL Models
Detailed mappings of device pins and functions used for PCB layout, routing, and system integration.
- Virtex™, Kintex™, Artix™ UltraScale™ and UltraScale+™ Package Files
- Spartan™ 7 FPGA Package Files
- Virtex™ 7 FPGA Package Files
- Kintex™ 7 FPGA Package Files
- Artix™ 7 FPGA Package Files
- Virtex™ 6 FPGA Package Files
- Spartan™ 6 FPGA Package Files
- Virtex™ 5 FPGA Package Files
- Virtex™ 4 FPGA Package Files
Files used for JTAG-based boundary scan testing to validate connectivity and enable board-level debugging and manufacturing test.
BSDL Models for Versal™, Zynq™ UltraScale+™, and Zynq™ 7000 SoCs; and UltraScale+, UltraScale™, and 7 series FPGAs
BSDL Model file (ZIP - 26.28 MB)
MD5 SUM Value : 1f84fd88930411c4afab66c1a0c570ef
Last Updated: Mar 26, 2026
Download Verification
For details on how to verify, please refer to UG973 - Release Notes, Installation, and Licensing.
BSDL Models Archive for mature FPGAs, CPLDs, and PROMs
BSDL Model Archive files (ZIP - 27.56 MB)
MD5 SUM Value : c899ffc40a2ad0145424c703f589b00b
Last Updated: Feb 12, 2024