Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
by: AMD
The AXI-4 Stream to Video Out LogiCORE™ IP core converts AXI4-Stream interface signals to a standard parallel video output interface with timing signals.
Included at no additional charge with Vivado™ software.
AXI4-Stream to Video Out IP core enables video designers to quickly and easily connect video processing blocks that use AXI4-Stream to external video sinks.
The AXI-4 Stream to Video Out LogiCORE™ IP core converts AXI4-Stream interface signals to a standard parallel video output interface with timing signals. The AXI4-Stream interface accepts signals that are compliant to the AXI4-Stream Video Protocol as defined in the AXI Reference Guide (UG761), and as is implemented on most AMD Video IP cores. The output interface is suitable for use with many external video sinks and contains standard video timing signals including Vsync, Hsync, Vblank, Hblank, DE and pixel clock. This enables video designers to quickly and easily connect video processing blocks with an AXI4-Stream interface to an external video sink such as a DVI PHY. This core works in conjunction with the AMD Video Timing Controller (VTC) core to generate the video format timing signals. Source code is provided with the core to allow customers to adapt the core to work with unique video signals that may not already be included in the core.
LogiCORE™ | Version | AXI4 Support | Software Support | Supported Device Families |
---|---|---|---|---|
AXI4-Stream to Video Out | v4.0 | AXI4-Stream | Vivado™ 2025.1 | Kintex™ UltraScale+™ Virtex™ UltraScale+ Zynq™ UltraScale+ Kintex UltraScale™ Virtex UltraScale Zynq 7000 Artix™ 7 Kintex 7 Virtex 7 |
AXI4-Stream to Video Out | v2.01a | AXI4-Stream | ISE™ 14.3 | Zynq 7000 Artix 7 Kintex 7 Virtex 7 Virtex 6 HXT / LXT / SXT Spartan™ 6 LXT / LX |
Download the required software from the AMD Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.
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