View release highlights for previous versions of AMD Vitis™ here.

AMD Vitis™ Software Platform 2026.1 Release Highlights

Enhanced Design Flow with Versal™ AI Engines

  • New and Enhanced DSP Library Functions
    • New Forward and Backward Substitution
    • New Cholesky Decomposition
    • New QRD (Modified Gram-Schmidt and Householder)
    • New Singular Value Decomposition (SVD)
    • Enhanced Channelizers with Packet Switching IP
    • Enhanced 1D FFT using AI Engine + PL
    • Enhanced FIR, FFT, and GeMM performance
  • AI Engine API Enhancements for Versal AI Edge Series Gen 2 (AIE-ML v2)
    • New FP8 data types (bfloat8 and float8)
    • New caccfloat data type for complex accumulation operations
    • Support for matrix multiply, MAC, sliding_mul_ops and ADF graph applications
  • Improved AI Engine Compiler
    • Production release of AI Engine kernel code coverage
    • Per-kernel Xchess pragma support (Early Access)
    • Read-only shared buffer support with compile-time initialization
    • Runtime update support for read-only shared buffers
    • Improved memory tile programming model
    • Enhanced mapper and router QoR
    • Column-based mapping for more compact implementations
    • Automatic stamp-and-repeat placement for reusable subgraphs

Easier Verification of Versal AI Engine Designs

AMD Vitis Hardware in the Loop (Vitis HIL) (Production Release)

  • Production-ready Vitis HIL
  • MATLAB® and Python™ testbench support
  • Supports VCK190 and VEK280 development kits
  • Accelerates full-system AIE + PL verification using real hardware

Vitis Functional Simulation

  • Functional simulation using MATLAB®, Python™ and C++ (Early Access)
  • Verification of AI Engine graphs, HLS kernels and AIE+PL subsystems
  • Bit-accurate simulation
  • Support for heterogeneous verification workflows
  • Versal RF hard block support
  • FFT, Channelizer and Down Conversion support
  • Enhanced C/C++ varray APIs
  • Additional Vitis HLS support:
    • HLS tasks
    • HLS IP libraries (FFT, FIR, dsp_builtins)
    • burst_maxi library
    • AXI side channels
  • LogicCore IP support including xFFT and FIR Compiler
  • Standalone Vitis Functional Simulation package (EA)

Enhancements to Vitis Model Composer for AIE DSP Designs

New AI Engine DSP Library Blocks

  • Function Approximation
  • Hadamard Transform
  • Kronecker Product
  • Outer Tensor Product
  • GEMM / GEMV

Enhanced HDL Library Blocks

  • Enhanced FIR Compiler
  • Complex data type support for Versal devices
  • DSP58 9x8 dot-product mode
  • DSPFP32 support
  • Vector xFFT
  •  SSR FFT support

Versal RF Hard IP Support

  • FFT
  • Channelizer
  • LDPC Decoder
  • RFDC
  • RTL simulation using XSIM
  • SystemC/TLM models for FFT and Channelizer

Additional Vitis Model Composer Enhancements

  • Programmatic access to AI Engine kernel, graph and class kernel configuration
  • FFT/IFFT buffer constraints
  • Graph iteration control for AI Engine simulation
  • Support for MATLAB® R2026a
  • Support for RHEL 9.7 and Ubuntu 24.04.3 LTS

Expanded LogiCORE™ PL DSP IP

New PL DSP IP Enhancements

  • FIR native support for DSPCPLX complex DSP primitive
    • Integer-rate decimation
    • Fractional-rate interpolation
    • Fractional-rate decimation
  • FIR native support for DSPFP32
  • PL xFFT support with VSS AI Engine flow
  • New Mixed-Radix FFT IP (EA)
  • New Transposer IP (EA)
  • Wide 35x18 Complex MAC using cascade (EA)

Updates for Vitis IDE for Embedded Development

Ease-of-Use and Debug Enhancements

  • Vitis System Level Trace (System Timeline)
    • Unified visibility across PL, PS and AI Engines
  • Vitis Analyzer UI enhancements
  • Multi-partition AI Engine analysis support
  • Updated system design examples delivered directly from GitHub
  • AI Engine Test Harness support for VEK385 and VRK160 (EA)

Enhanced Vitis Subsystem (VSS) Integration

  • Expanded VSS Integration Project support
  • Support for nested and mixed VSS flows
  • Python CLI support for scripted workflows

Static and Dynamic Library Support

  • Improved code reuse across applications
  • Broader processor coverage
  • Debug support and templates

AI-Powered Development

  • Production release of Theia AI Chat
  • Support for OpenAI, Anthropic and Google model providers through customer-supplied API keys

Vitis What's New by Category

Expand the sections below to learn more about the new features and enhancements in AMD Vitis software platform 2026.1. For information on supported platforms, changed behavior, and known issues, please refer to the Vitis software platform 2026.1 Release Notes for the Application Acceleration Flow and Embedded Software Development Flow.

Enhanced DSP Library Functions:

  • New Forward and Backward Substitution
  • New Cholesky Decomposition
  • New QRD (Modified Gram-Schmidt and Householder)
  • New Singular Value Decomposition (SVD)
  • Enhanced Channelizers with Packet Switching IP
  • Enhanced 1D FFT using AI Engine + PL
  • Enhanced FIR, FFT and GeMM performance

Applies to:

  • Versal™ AI Core with AIE
  • Versal AI Edge with AIE-ML
  • Versal AI Edge Series Gen 2 with AIE-ML v2

Vitis Hardware-in-the-Loop (Production Release)

  • Production-ready Hardware-in-the-Loop (HIL)
  • MATLAB® and Python™ testbench support
  • Supports VCK190 and VEK280 development kits
  • Accelerates full-system AIE + PL verification using real hardware

Vitis Functional Simulation

  • Functional simulation using MATLAB®, Python™ and C++ (Early Access)
  • Verification of AI Engine graphs, HLS kernels and AIE+PL subsystems
  • Bit-accurate simulation
  • Support for heterogeneous verification workflows
  • Versal RF hard block support
  • FFT, Channelizer and Down Conversion support
  • Enhanced C/C++ varray APIs
  • Additional Vitis HLS support:
    • HLS tasks
    • HLS IP libraries (FFT, FIR, dsp_builtins)
    • burst_maxi library
    • AXI side channels
  • LogicCore IP support including xFFT and FIR Compiler
  • Standalone Vitis Functional Simulation package (EA)

New AI Engine DSP Library Blocks

  • Function Approximation
  • Hadamard Transform
  • Kronecker Product
  • Outer Tensor Product
  • GEMM / GEMV

Enhanced HDL Library Blocks

  • Enhanced FIR Compiler
  • Complex data type support for Versal devices
  • DSP58 9x8 dot-product mode
  • DSPFP32 support
  • Vector xFFT
  • SSR FFT support

Versal RF Hard IP Support

  • FFT
  • Channelizer
  • LDPC Decoder
  • RFDC
  • RTL simulation using XSIM
  • SystemC/TLM models for FFT and Channelizer

Additional Vitis Model Composer Enhancements

  • Programmatic access to AI Engine kernel, graph and class kernel configuration
  • FFT/IFFT buffer constraints
  • Graph iteration control for AI Engine simulation
  • Support for MATLAB® R2026a
  • Support for RHEL 9.7 and Ubuntu 24.04.3 LTS

Array Partition Library (hls_array_partition.h) – New library allows you to explicitly define parallel accesses and helps compiler to make certain access-related decisions

  • Offers a more user-friendly approach and guarantees parallel execution when data patterns allow

Optimized Unaligned Burst

  • Improvement to hls_burst_maxi that adds support for unaligned memory accesses and non-power-of-2 access types (for example: 24-bit RGB)

Vitis IDE Supports the AI Features Added by Theia

  • New AI features introduced directly in the Vitis Unified IDE based on Theia
  • Users can add your API key and skills through settings and access the AI features

Ease of Use Enhancements

  • Expanded support for the LogiCORE IP including multi-channel FIR and Versal RF FFT (EA)
Footnotes
  1. Based on testing on August 10, 2023, across 1000 Vitis L2/L3 code library designs, with Vitis HLS release 2023.2 vs. Vitis HLS 2023.1. System configuration during testing: Intel Xeon E5-2690 v4 @ 2.6GHz CPU, 256GB RAM, RedHat Enterprise Linux 8.6. Actual performance will vary. System manufacturers may vary configuration, yielding different results. -VGL-04
  2. The benchmark tests were performed on all 1208 Vitis L1 library C-code designs as of February 12th, 2023. All designs were run using a system with 2P Intel Xeon E5-2690 CPUs with CentOS Linux, SMT enabled, Turbo Boost disabled. Hardware configuration not expected to effect software test results. Results may vary based on software and firmware settings and configurations- VGL-03