SEV Ciphertext Side Channel Attacks
Summary
AMD has received reports from two research groups detailing methods by which a malicious hypervisor could potentially execute a side channel attack against a running secure encrypted virtualization – secure nested paging (SEV-SNP) guest.
The first report, titled “Relocate + Vote: Exploiting Ciphertext Side-Channels using Sparsity Information,” was submitted by researchers at the Toronto System Security Lab of the University of Toronto. In their paper, the researchers propose using management commands that allow the hypervisor to move or swap guest pages, combined with the hypervisor’s ability to view guest ciphertext, to potentially execute a side-channel attack that could compromise the confidentiality of SEV-SNP guest data.
A subsequent report from researchers at ETH Zurich titled “Chosen Plaintext Oracle against SEV-SNP," outlines a similar exploitation technique that also leverages the ability to move or swap guest pages.
The security features of SEV-SNP for 3rd and 4th generation EPYC™ processors do not limit the hypervisor’s ability to view guest ciphertext. This behavior is documented in the public whitepaper “SEV-SNP – Strengthening vm Isolation with Integrity Protection and More” (for link, please see the references section below). AMD has previously detailed the potential of ciphertext side channel attacks on SEV. For more information, please see AMD-SB-1033, and the AMD paper “Technical Guidance for Mitigation Effects of Ciphertext Visibility Under AMD SEV” (for links to both, please see the References section below).
Mitigation
While ciphertext visibility is a known potential side-channel in SEV-SNP, AMD believes there are steps that can be taken to make exploitation of these types of side channel attacks more difficult. The ability of the hypervisor to move or swap guest pages can be disabled via guest-specific policy controls in SEV-SNP. For more information about configuring this option, please review the SEV Secure Nested Paging Firmware ABI Specification version 1.58 or later (for link, please see references section below) or contact your cloud service provider.
Additionally, AMD has introduced ciphertext hiding starting with 5th generation EPYC processors (formerly codenamed “Turin”). Ciphertext hiding limits the hypervisor’s ability to view guest ciphertext during guest execution, reducing the potential risk of ciphertext side channels. For more information about this feature, please review the SEV Secure Nested Paging Firmware ABI Specification (for link, please see references section below).
For more information on best-practices regarding ciphertext side-channel attacks, see our whitepaper “Technical Guidance for Mitigation Effects of Ciphertext Visibility Under AMD SEV” and our previous security bulletin on this topic, AMD-SB-1033. Links to both documents are available in the References section below.
References
Acknowledgement
AMD thanks the following for reporting this issue and engaging in coordinated vulnerability disclosure:
Yuqin Yan of the University of Toronto
Wei Huang of the University of Toronto & Seneca Polytechnic
Ilya Grishchenko of the University of Toronto
Gururaj Saileshwar of the University of Toronto
Aastha Mehta of the University of British Columbia
David Lie of the University of Toronto
AMD also thanks the following for their subsequent report and engaging in coordinated vulnerability disclosure:
Benedict Schlüter, Supraja Sridhara, Christoph Wech, and Shweta Shinde of ETH Zurich
Revisions
| Revision Date | Description |
| 2025-08-12 | Initial publication |
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