Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
by: AMD
The AMD Versal™ programmable network on chip (NoC2) is an AXI-interconnecting network used for sharing data between IP endpoints in the programmable logic (PL), the processing system (PS), and integrated DDR5/LPDDR5/LPDDR5X memory controller.
The AMD Versal™ programmable network on chip (NoC2) is an AXI-interconnecting network used for sharing data between IP endpoints in the programmable logic (PL), the processing system (PS), and other integrated blocks. This device-wide infrastructure is a high-speed, integrated data path with dedicated switching. The NoC can be logically configured to represent complex topologies using a series of horizontal and vertical paths and a set of customizable architectural components.
The integrated memory controller supports DDR5, LPDDR5, and LPDDR5X memory interfaces. It supports a wide range of component and DIMM topologies. It has two programmable NoC interface ports and is designed to handle multiple streams of traffic. Quality of Service (QoS) classes are available to ensure appropriate prioritization of commands. The controller accepts burst transactions and implements command reordering to maximize efficiency of the memory interface. Optional external interface reliability and security features include ECC error detection/correction and inline encryption/decryption.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.