Performance Counter Side Channel

Bulletin ID:     AMD-SB-3013
Potential Impact: N/A
Severity: N/A

Summary

Researchers from Graz University of Technology, Austria, have reported a way for a malicious hypervisor to monitor performance counters and potentially recover data from a guest VM.

Mitigation

Performance counters are not protected by SEV, SEV-ES, or SEV-SNP.  AMD recommends software developers employ existing best practices, including avoiding secret-dependent data accesses or control flows where appropriate to help mitigate this potential vulnerability.  AMD has defined support for performance counter virtualization in APM Vol 2, section 15.39.  PMC virtualization, planned for availability on AMD products starting with “Zen 5”, is designed to protect performance counters from the type of monitoring described by the researchers.

Acknowledgement

AMD thanks the following for reporting this issue and engaging in coordinated vulnerability disclosure:
Stefan Gast, Hannes Weissteiner, and Daniel Gruss of Graz University of Technology, Austria
Robin Leander Schröder from Fraunhofer SIT (Darmstadt) / Fraunhofer Austria (Vienna)

Revisions

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