AMD SEV Incomplete Cleanup Vulnerability

Summary

A security researcher reported a flaw in VMRUN error handling that may expose Secure Encrypted Virtualization -Secure Nested Paging (SEV-SNP) guest register data to a privileged attacker via a Transient Scheduler Attacks (TSA) side channel attack resulting in a loss of confidentiality. AMD has assessed the report and plans to release mitigations.

CVE Details

Refer to Glossary for explanation of terms 

CVE

CVE Description

CVSS Base Score

CVE-2026-40671

Incomplete cleanup during VMRUN error handling could allow access to a Secure Encrypted Virtualization-Secure Nested Paging (SEV-SNP) guest register state, potentially resulting in information disclosure and impacts to confidentiality.

4.9
CVSS:4.0/AV:L/AC:L/AT:N/PR:H/UI:N/VC:L/VI:N/VA:N/SC:N/SI:N/SA:N
CWE- 459: Incomplete Cleanup

Specific CVSS scores may change subject to your implementation. We encourage you to calculate CVSS scores independently for your system.

Affected Products and Mitigation

AMD plans to release to the Original Equipment Manufacturers (OEM) the Platform Initialization (PI) firmware versions on the target dates listed below. Please contact your OEM for the BIOS update specific to your product(s).

*Note: Products believed to not be affected by the listed CVEs are not included.AMD EPYC™ Series Processors

AMD EPYC™ Series Processors

Product

CVE ID

Platform Initialization (PI) Mitigation

PI Release Date

Microcode Mitigation

Microcode Release Date

AMD EPYC™ 7003 Series Processors

CVE-2026-40671

MilanPI-SP3_1.0.0.L

Target release planned for Nov'26

Milan-B1 0x0A0011E1

Milan-B2 0x0A00124E

2026-08-12

AMD EPYC™ 8004 Series Processors

CVE-2026-40671

Genoa_100J Patch 3

Target release planned for Nov'26

Siena RSDN - A2 0x0AA0021F

2026-08-12

AMD EPYC™ 8005 Series Processors

CVE-2026-40671

TurinPI_1.0.0.C

Target release planned for Nov'26

0x0B002176

2026-08-12

AMD EPYC™ 9004 Series Processors

CVE-2026-40671

Genoa_100J Patch 3

Target release planned for Nov'26

Genoa RS-B1 0x0A10115B

Genoa-RS-B2 0x0A10125B

2026-08-12

Bergamo RSDN-A2 0x0AA0021F

2026-08-12

AMD EPYC™ 9005 Series Processors

CVE-2026-40671

TurinPI_1.0.0.C

Target release planned for Nov'26

Turin Classic -BRH C1 0x0B002176

Turin Dense - BRH D B0 0x0B101067

2026-08-12

AMD Instinct™ Accelerators

Product

CVE ID

Platform Initialization (PI) Mitigation

PI Release Date

Microcode Mitigation

Microcode Release Date

AMD Instinct™ MI300A Series Processors

CVE-2026-40671

Patch version 0x0A900110

2026-09-21

0x0A900110

2026-09-21

AMD EPYC™ Embedded Series Processors

Product

CVE ID

Mitigation

Mitigation Release Date

AMD EPYC™ Embedded 7003 Series Processors

CVE-2026-40671

Version TBD

Target release planned for Jan'27

AMD EPYC™ Embedded 8004 Series Processors

CVE-2026-40671

Version TBD

Target release planned for Apr'27

AMD EPYC™ Embedded 9004 Series Processors

CVE-2026-40671

Version TBD

Target release planned for Apr'27

AMD EPYC™ Embedded 9005 Series Processors

CVE-2026-40671

Version TBD

Target release planned for Feb'27

Acknowledgement 

AMD thanks the following for reporting and engaging in coordinated vulnerability disclosure:

  • Alessandro Vezz`u1, Benedict Schluter, Shweta Shinde ETH Zurich, Daniel Moghimi Google: CVE-2026-40671

Revisions

Revision Date Description
2026-11-10 Initial version

DISCLAIMER

The information contained herein is for informational purposes only and is subject to change without notice. While every precaution has been taken in the preparation of this document, it may contain technical inaccuracies, omissions and typographical errors, and AMD is under no obligation to update or otherwise correct this information. Advanced Micro Devices, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this document, and assumes no liability of any kind, including the implied warranties of noninfringement, merchantability or fitness for particular purposes, with respect to the operation or use of AMD hardware, software or other products described herein. Any computer system has risks of security vulnerabilities that cannot be completely prevented or mitigated. No license, including implied or arising by estoppel, to any intellectual property rights is granted by this document. Terms and limitations applicable to the purchase or use of AMD's products are as set forth in a signed agreement between the parties or in AMD's Standard Terms and Conditions of Sale.

AMD, the AMD Arrow logo, EPYC, Instinct, and combinations thereof are trademarks of Advanced Micro Devices, Inc. CVE is a trademark of The MITRE Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Third party content may be licensed to you directly by the third party that owns the content and is not licensed to you by AMD. ALL LINKED THIRD-PARTY CONTENT IS PROVIDED 'AS IS' WITHOUT A WARRANTY OF ANY KIND. USE OF SUCH THIRD-PARTY CONTENT IS DONE AT YOUR SOLE DISCRETION AND UNDER NO CIRCUMSTANCES WILL AMD BE LIABLE TO YOU FOR ANY THIRD PARTY CONTENT. YOU ASSUME ALL RISK AND ARE SOLELY RESPONSIBILITY FOR ANY DAMAGES THAT MAY ARISE FROM YOUR USE OF THIRD-PARTY CONTENT.

© 2026 Advanced Micro Devices, Inc. All rights reserved.