AMD Spartan™ UltraScale+™ XA FPGAs Product Advantages

With more devices and sensors connected at the edge, there is a need for secure devices that can handle large amounts of data. The new, cost-optimized, high I/O Spartan UltraScale+ XA FPGAs help automotive designers rapidly move through challenges of delivering low cost, power efficiency, and modern security features to build camera and LiDAR systems.

Tried. Trusted. Long Lasting.

With typical lifespans extending well past 15 years, you can depend on AMD devices for the life of your design—extending AMD 7 Series FPGAs and adaptive SoCs through 2040 and AMD UltraScale+™ FPGAs and adaptive SoCs through 2045.

 

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High I/O, Low-Power & State-of-the-Art Security Features
  • Industry’s highest I/O-to-logic cell ratio in FPGAs built in 28 nm and lower process technology1
  • 16 nm FinFET process delivers up to 30% lower total power consumption versus the previous generation2
  • The XASU35P device offers MIPI D-PHY support with lane rate of up to 2.5 Gb/s, meeting the necessary data rate for cloud point generation
Faster Design Convergence with Proven Design Tools
  • Robust and high-quality AMD Vivado™ Design Suite in production since 2012
  • Single tool covering simulation to verification for entire FPGA portfolio
Design Once with a Trusted Supplier
  • Nearly 40 years in the FPGA business with billions of devices shipped
  • Over 15 years product lifecycle, and in-field upgradeability for maximum design longevity

Fundamental Building Block

The Spartan UltraScale+ XA FPGAs present advanced I/O capabilities, low-power consumption, and state-of-the-art security features, ideal to implement automotive designs at the edge.

Spartan UltraScale+ XA FPGAs diagram

Product Table

  XA SU35P
System Logic Cells (K) 36
CLB LUTs (K) 16
DSP Slices 48
Total RAM (Mb)* 1.93
Integrated Memory Controller LPDDR4X/5 0
Transceivers (16.375 Gb/s or 12.5 Gb/s) 0
PCI Express® 0
Maximum I/O Pins 304

* Total RAM = Maximum Distributed RAM + Total Block RAM + Total UltraRAM 

Verify all data in the above table with the device data sheets or product guides.

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Footnotes
  1. Highest I/O-per-logic-cell is based on an AMD internal analysis of the product data sheet for AMD Spartan UltraScale+ SU10P FPGA and the published product data sheets for comparable competitive FPGAs with a 28 nm and lower node-size, from Efinix, Intel, Lattice, and Microchip. Cost reduction per I/O is based on AMD list prices for the AMD Spartan UltraScale+ SU10P versus the AMD Spartan 7 7S50, as of February 2024, for designs requiring at least 200 GPIO. (SUS-011)
  2. Projection is based on AMD labs internal analysis in January 2024, using total power calculation (static plus dynamic power) based on the difference in logic cell count of an AMD Artix UltraScale+ AU7P FPGA, to estimate the power of a 16 nm AMD Spartan UltraScale+ SU35P FPGA versus a 28 nm AMD Artix 7 7A35T FPGA, using Xilinx Power Estimator (XPE) tool version 2023.1.2. Total power estimates and projections will vary when products are released in market and based on design, configuration, usage, and other factors. (SUS-003)