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LVDS Tunneling Protocol & Interface (LTPI) IP

The LTPI IP is designed to be used inside a data center server to enable the mapping and transport of various low speed I/O interfaces (known as channels) such as a GPIO, UART, I2C/SMBus, OEM and memory mapped data channel (that is, AXI4-Lite) via a high-speed Low Voltage Differential Signaling (LVDS) serial link.

Part Number:
- EF-DI-LTPI-SITE
Design Tools Support: Vivado Software
License: Core License Agreement
Device Support: Artix 7, Kintex 7, Kintex UltraScale+, Artix UltraScale+, Spartan 7, Spartan UltraScale+

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Overview
Documentation
Order
Supported Tool Version

Product Description

The LTPI IP is designed to enable the mapping and transport of various low speed I/O interfaces (known as channels) such as a GPIO, UART, I2C/SMBus, OEM and memory mapped data channel (that is, AXI4-Lite) via a high-speed Low Voltage Differential Signaling (LVDS) serial link. For systems incorporating OCP DC-SCM specifications, LTPI can enable more signals to be shared between the BMC module (SCM) and the Host processor module (HPM). The LVDS interface is designed for low cost and low power FPGAs, making it ideal for resource constrained designs. As an industry standard protocol, LTPI ensures broad compatibility and long-term support across vendors. Additionally, LTPI's configurable and scalable architecture allows designers to customize the interface to meet varying performance and integration needs.

Key Features and Benefits

Compliant with OCP LTPI Specification
All standard LTPI rates starting from 25 Mb/s (25 MHz SDR):
- Up to 800 Mb/s (400 MHz DDR) for AMD 7 series devices
- Up to 1.2 Gb/s (600 MHz DDR) for AMD UltraScale+™ series devices
General purpose I/O (GPIOs):
- 16 LL GPIOs
- Up to 1008 NL GPIOs
Up to two universal asynchronous receiver-transmitter (UART) channels
Up to six I2C/SMBus channels:
- Each I2C/SMBus interface can be configured as either a controller or a target
Optional OEM channel:
- Up to 32 bits of OEM data
Optional data channel
- When enabled, it is interfaced through the AXI4-Lite slave on SCM and AXI4-Lite master on HPM.

Documentation

Vivado IP Release Notes

This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.

View Release Note

PG448 - LogiCORE LTPI (v3.0) Product Guide

View Product Guide

LTPI LogiCORE™ IP

Full access to this IP core, including bitstream generation capability, requires that you generate and install a Full License Key.

Requirements

Please refer to the Requirements link on the product page for this core for information on:

Software and system requirements
Licensing terms and conditions for evaluation

License Terms

This core is licensed under the following terms: Core License Agreement.

Ordering Information

To purchase a LogiCORE™ IP core, contact your local Sales Representative referencing the part number in the table below:

LogiCORE Product Name	Part Number
LTPI	EF-DI-LTPI-SITE

Generate and Install a Full License Key

After purchasing a license for this core, follow the instructions in the purchase confirmation email you will receive on downloading the IP core netlist from the Licensing Site, and on generating and installing a Full license key to activate Full access to the core.

Release Notes & Known Issues

For information on New Features, Known Issues, and Patches please refer to the Installation, Licensing and release Notes document available on the Licensing Solution Center.