Building the Classical Foundation for Fault-Tolerant Quantum Computing

Nov 09, 2026

A new survey brings together expertise from AMD, HPE, IBM, IQM, Riverlane, and Xanadu to help the community navigate hierarchical QEC decoding.

AMD powers the world's leading scientific computing, from the exascale supercomputers driving discovery in the United States and Europe to Lux, the first Genesis Mission system for AI-driven science. With leadership CPUs, GPUs, FPGAs, networking and open ROCm software, AMD gives nations, laboratories and enterprises a single open platform for high-performance computing, AI for science, sovereign AI, agentic AI and the path to quantum computing.

Quantum error correction is a key part of that path, connecting reliable quantum operations with the classical computing needed to support them.

Delivering on the promise of quantum computing means building machines that can carry out long, reliable computations. Quantum error correction (QEC) is central to that goal. By protecting logical information across physical qubits, it creates a path toward the low logical error rates that useful applications will require. Making that protection work requires classical computing systems that interpret error information, keep pace with the quantum processor, and provide correction information when needed by subsequent quantum operations.

That challenge brings quantum algorithms, classical hardware, and system design together. How should decoding work be organized as quantum systems scale? Which tasks benefit from specialized hardware? When can multiple decoding stages improve efficiency, and when is a single decoder the right choice?

Our survey, Hierarchical Decoding for Quantum Error Correction, brings together researchers from AMD, HPE, IBM, IQM, Riverlane, and Xanadu to examine these questions. It connects a broad decoding literature to the practical decisions facing quantum system builders, giving researchers and engineers a shared starting point for exploring algorithms, code constructions, and hardware implementations.

Making a growing field easier to navigate

The decoding community has developed a rich set of approaches, from algorithms that solve a decoding task directly to designs that distribute work across stages, processors, or encoding layers. Understanding how these approaches relate is essential to choosing a design that fits a particular quantum system.

The survey organizes this landscape into three connected areas. First, it examines decoders for a single code and extensions such as predecoding, sliding windows, streaming, and distributed execution. Second, it explores hierarchical and concatenated codes, where inner and outer decoders follow the layers of the encoding. Third, it connects these choices to implementations on CPUs, GPUs, FPGAs, ASICs, and cryogenic platforms.

This organization makes it easier to see where ideas can transfer between designs and where the underlying assumptions differ. A fast initial stage, for example, may handle common error patterns and reduce the work passed to a subsequent decoder. In a concatenated code, an inner decoder may instead pass information about the reliability of its decisions to an outer decoder. Both involve information exchange, but they solve different design problems.

Turning decoding ideas into system choices

For system builders, a decoder’s value depends on how it performs within the complete quantum computer. Accuracy determines whether it can support the application’s logical error target. Throughput determines whether it can keep up with incoming error information. Communication, memory, power, and cooling requirements determine how broadly the design can be deployed as the number of logical qubits grows.

The HPE team brought a systems perspective focused on what large-scale fault-tolerant quantum computers will need from their classical infrastructure. That includes keeping the end-to-end path, from qubit readout to correction, fast enough while fitting complex decoding strategies into complete computing architectures as the number of logical qubits grows. They are focused on pushing the throughput of the fastest known decoders, such as belief-propagation, while studying the latency-accuracy trade-offs with more powerful maximum likelihood decoders on rarer error events.

“Fault-tolerant quantum computing will depend on high-performance classical systems that can process error information in real time and at scale, making decoding as much a systems problem as an algorithmic one. This survey connects the decoding literature to the accuracy, latency, communication, and energy trade-offs that system architects face, and identifies where better benchmarks and tighter integration are still needed. At HPE, we see the co-design of algorithms and computing architecture as essential to incorporating quantum error correction into scalable quantum supercomputers.” — Masoud Mohseni, Senior Distinguished Technologist, Director of HPE Quantum

“IBM’s advances in quantum error correction and decoding are helping define what’s needed to build a practical, useful fault-tolerant quantum computer. As we move from theory toward real systems, we need to co-design the error-correcting codes, decoding algorithms, and classical infrastructure to work together efficiently at scale. This survey is an important step toward helping the field get there.” — Blake R. Johnson, Distinguished Engineer, QEC Infrastructure, at IBM.

Latency matters across the full path from qubit readout to correction information usable by the control system. Decoder runtime is one part of that path; data movement and waiting for resources also contribute. Where buffering and the computation’s schedule permit, occasional slower results can be accommodated. When a later logical operation depends on a result, that delay can hold up the computation. These differences make the complete system context essential to evaluating a reported performance number.

“Hierarchical decoding is one of the most active areas in quantum error correction, and this survey shows how wide the design space has become. Timing requirements span roughly three orders of magnitude across qubit platforms, from microsecond superconducting cycles to millisecond-scale trapped-ion requirements. Hierarchy, whether across decoding stages, time windows, and devices or in layered codes, gives engineers more room to balance accuracy, speed, bandwidth, and cost. At Riverlane, we see QEC as one of the most demanding real-time data processing problems in computing, which is why we built Deltaflow to work across every major qubit modality. The next step for the field is measuring these trade-offs end to end, from qubit readout to usable correction.” — Elise Jennings, Principal Investigator for High Performance Computing & Quantum, Riverlane

The survey preserves the evaluation conditions of published studies, helping readers understand what a result demonstrates and how it applies to their own system. Its contribution is a connected view of the design space: the opportunities offered by specialization and parallelism, the information that must move between stages, and the overheads that can offset the benefits. That view can guide prototype development, hardware selection, and more informative performance reporting.

Bringing AMD compute capabilities to the quantum ecosystem

These design choices align with the broader approach to quantum computing at AMD: provide classical computing technologies that researchers and system builders can combine around their requirements. AMD CPUs, Instinct™ GPUs, FPGAs, and adaptive SoCs offer different capabilities for implementing and integrating decoding workloads. Programmable logic can support specialized processing close to the control path, while CPUs and GPUs provide options for flexible software and parallel computation. The appropriate combination depends on the algorithm, data movement, and timing needs of the system. [1]

The collaboration between Xanadu and AMD on Backline provides a concrete example of this integration effort. Backline connects quantum workloads with classical computing resources, including AMD processors, accelerators, and adaptive hardware. It illustrates why communication and orchestration deserve attention alongside the decoding algorithm itself. [2]

“Hierarchical decoding is as much a systems problem as an algorithms one, and this survey is careful to keep track of what each result actually measured,” said Josh Izaac, Sr. Staff Quantum Scientist at Xanadu. “It also makes clear that decoding won’t all happen in one place. The right split depends on the QEC code, the hardware, and the program, and that answer will keep changing.

“At Xanadu we’re coming at this from the program and infrastructure side. With AMD, we built Backline so that choosing a decoder, or moving it from a CPU to a GPU, means editing a few lines of a PennyLane program instead of rewriting it. You can even debug a hierarchical decoder on a laptop before going anywhere near real hardware.”

By contributing to this survey, AMD is helping connect those implementation capabilities with the broader research community’s understanding of QEC. The goal is to make promising decoding approaches easier to evaluate, implement, and develop into complete systems.

A shared foundation for the next stage of QEC

Progress toward fault-tolerant quantum computing depends on bringing advances in codes and algorithms into systems that can operate reliably at scale. This survey gives the community a common vocabulary for that work and identifies where clearer measurements and tighter integration can make the next generation of designs more useful.

“Every decoder ultimately answers to the quantum processor. On superconducting hardware, syndrome data arrives about every microsecond, and the resulting logical observation only counts once the control system can act on it. Some qLDPC codes are significantly more efficient with respect to physical qubit count, but they are harder to decode. Hierarchical decoding, with fast stages close to the control system and more powerful decoders behind them, can help that saving hold up on real hardware. Getting there takes full-stack engineering and open architectures that let researchers bring their own decoders to the machine. That combination is what will make fault-tolerant quantum computing a reality.” — Johannes Heinsoo, Principal Engineer and Head of QEC Architecture & Implementation, IQM

For researchers, it offers connections across areas that are often studied separately. For system builders, it provides a guide to the questions that matter when turning a decoding result into an implementation. Together, these perspectives can help the community focus its efforts on the classical infrastructure that scalable quantum computing needs.

Learn more about AMD quantum computing technologies: https://www.amd.com/en/solutions/quantum-computing.html

We thank our collaborators at HPE, IBM, IQM, Riverlane, and Xanadu for their contributions to the survey. See our paper, Hierarchical Decoding for Quantum Error Correction, for the full author list and technical discussion.