High I/O, Low-Power FPGAs with State-of-the-Art Security Features
With typical lifespans extending well past 15 years, you can depend on AMD devices for the life of your design—extending AMD 7 Series FPGAs and adaptive SoCs through 2040 and AMD UltraScale+™ FPGAs and adaptive SoCs through 2045.
With more devices and sensors connected at the edge, there's a need for secure devices that can handle large amounts of data. The new cost-optimized high I/O AMD Spartan™ UltraScale+™ FPGA family helps designers rapidly move through these challenges by delivering low cost, power efficiency, and modern security features.
The Spartan UltraScale+ FPGA presents advanced I/O capabilities, low-power consumption, and state-of-the-art security features. Equipped with high-speed transceivers, substantial built-in and external memory, and PCIe® Gen4, this family provides robust solutions for a broad array of applications.
Take a deep dive into the high I/O, low power, and state-of-the-art security features of Spartan UltraScale+ FPGAs and learn how you can accelerate time to market with AMD, a trusted silicon supplier with proven design tools.
Spartan UltraScale+ FPGAs offer high GPIO counts, supporting both legacy and emerging protocols, and 16.3 Gb/s transceivers for networking, video, and vision applications. The devices are also in compliance with industry standards, such as PCIe® Gen4, 10 GE Vision, CoaXPress 2.1, and 12G-SDI, to help accelerate time to market.
Spartan UltraScale+ FPGAs leverage a 16 nm architecture and offer up to a 30% reduction in total power compared to the previous 28 nm devices on lower densities.2 The larger density devices, which include hard DDR and PCIe interfacing IP, offer an improved power efficiency of up to 60% compared to the previous 28 nm devices,3 thereby enhancing overall system performance.
Power delivery for Spartan UltraScale+ FPGAs is simplified by combining power rails together, reducing the amount of voltage regulators required, thus reducing sequencing complexity and shrinking BOM. AMD has partnered with industry-leading power vendors to ensure flexible power solutions from discrete regulators and LDOs to sophisticated Power Management ICs (PMICs) with integrated power sequencing. Leveraging AMD AECG power reference designs can also accelerate time to market and help ensure your power solution meets your design needs.
Explore our Simplified Power Sequencing application note for techniques on reducing power sequencing complexity and leveraging partner sequencers. Visit the AMD Power Efficiency page for more information.
Spartan UltraScale+ FPGAs provide robust, multi-tiered security with NIST-approved post-quantum cryptography, unique device-identification via the physical unclonable function, permanent tamper penalty for device protection, side-attack protection via DPA countermeasures, and adaptable AES-GCM decryption to meet evolving threats.
Complementing the energy efficiency, performance is enhanced by hard IPs, such as the integrated hard LPDDR4X/5 memory controller, available in select devices. This hard memory controller allows direct and high throughput access to up to 4.2 Gb/s of memory and reduces FPGA fabric resource utilization for high-value design blocks.
Featuring cost-optimized FPGAs that offer up to 3.2 Gb/s of MIPI performance, the Spartan UltraScale+ family supports advanced camera sensor capture and display. Complete MIPI IP and reference design solutions are also available here. The family’s LVDS performance also enables a range of other protocols, including SLVS-EC (for CMOS image sensors).
The production-proven UltraScale™ architecture, built on TSMC’s 16 nm low-power FinFET process, allows scalability to other 16 nm families as well as the broader portfolio. Developers can leverage the same IP, tool flow, and ecosystem to preserve design investment, enabling a reusable platform across a multi-product portfolio.
Spartan UltraScale+ FPGAs provide low-latency interfacing and processing for various sensors and connectivity standards of machine vision systems in industrial and medical fields. The FPGA family also offers compatibility with a wide range of communication protocols and are available in both compact and low-power devices.
As the demand for advanced data acquisition continues to grow in the market, the Spartan UltraScale+ FPGA offers flexible I/Os, on-chip memory, and efficient processing at the edge. Its low-power consumption, scalable networking, and advanced security features make it ideal for applications like sensor aggregation and point-of-care medical systems.
As server manufacturers’ motherboard designs are becoming more complex, the Spartan UltraScale+ FPGA can provide power management, flexible I/O, and reference designs, such as a general board-management controller, to address the data center server I/O market. The Spartan UltraScale+ FPGA is positioned as a family of devices that can scale with various server host processor motherboards and board management controller cards.
Harnessing the power of advanced broadcast technology, the Spartan UltraScale+ FPGA offers transformative capabilities. With PCIe® Gen4 and hard memory controllers LPDDR4x/5, these cards successfully ingest and transfer high-quality baseband video. Real-time transfer and high-efficiency processing simplify the video capture process and streamline the broadcasting workflow.
| SU10P | SU25P | SU35P | SU45P | SU60P | SU65P | SU100P | SU150P | SU200P | |
|---|---|---|---|---|---|---|---|---|---|
| System Logic Cells (K) | 11 | 22 | 36 | 53 | 66 | 66 | 101 | 138 | 219 |
| CLB LUTs (K) | 5 | 10 | 16 | 24 | 30 | 30 | 46 | 63 | 100 |
| DSP Slices | 24 | 36 | 48 | 96 | 144 | 144 | 144 | 384 | 384 |
| Total RAM (Mb)* | 1.77 | 1.84 | 1.93 | 3.03 | 4.10 | 4.37 | 5.98 | 11.65 | 26.79 |
| Integrated Memory Controller LPDDR4X/5 | 0 | 0 | 0 | 0 | 0 | 2 | 2 | 2 | 2 |
| Transceivers (16.375 Gb/s or 12.5 Gb/s) | 0 | 0 | 0 | 4 | 4 | 4 | 4 | 8 | 8 |
| PCI Express® | 0 | 0 | 0 | 1x Gen4x4 | 1x Gen4x4 | 1x Gen4x4 | 1x Gen4x4 | 1x Gen4x8 or 2x Gen4x4 |
1x Gen4x8 or 2x Gen4x4 |
| Maximum I/O Pins | 304 | 304 | 304 | 262 | 262 | 478 | 478 | 572 | 572 |
* Total RAM = Maximum Distributed RAM + Total Block RAM + Total UltraRAM
Verify all data in the above table with the device data sheets or product guides.
Jump-start your design cycle and achieve fast time to market with the proven hardware, software support, tools, design examples, and documentation available for the production silicon. Leverage the resources below to learn more about design tools and design methodologies for the UltraScale™ architecture.
The SCU35 Evaluation Kit, featuring the Spartan UltraScale+ SU35P FPGA, is an affordable development platform offering a wide range of sensor & peripheral interfacing options for diverse applications.
Find detailed specifications about the full UltraScale architecture product lines.
Learn more about how the AMD Vivado™ Design Suite accelerates the Spartan UltraScale+ design development with a push-button timing closure and fewer iteration cycles.
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