Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
by: AMD
The AMD UltraScale+™ Devices Integrated Block for PCI Express® (PCIe®) solution IP core is a high-bandwidth, scalable, and reliable serial interconnect building block solution for use with UltraScale+ devices.
The AMD UltraScale+™ Devices Integrated Block for PCI Express® (PCIe®) solution IP core is a high-bandwidth, scalable, and reliable serial interconnect building block solution for use with AMD UltraScale+ Devices. AMD offers three integrated blocks for PCIe in the AMD UltraScale+ Architecture: the PCIE4 integrated block, the PCIE4C integrated block, and the PCIE4CE integrated block. The PCIE4 block is found in the initially released AMD UltraScale+ devices. More recently released AMD UltraScale+ devices contain enhanced PCIE4C blocks or a mix of PCIE4C blocks and PCIE4 blocks. The AMD Spartan™ UltraScale+™ devices contain the PCIE4CE integrated block which is further enhanced. These blocks support 1-lane, 2-lane, 4-lane, 8-lane, and 16-lane configurations, including Gen1 (2.5 GT/s), Gen2 (5.0 GT/s) and Gen3 (8 GT/s) speeds. The PCIE4C block adds compatibility at Gen4 (16 GT/s) speeds up to 8-lane configurations, and the PCIE4CE block further adds compliance at Gen4 (16 GT/s) speeds up to 8-lane configurations.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.