Rapid Validation on AMD Versal Silicon without Leaving MATLAB or Python

Introducing AMD Vitis™ Hardware in the Loop

Validate Faster. Deliver Sooner.

AMD Vitis™ Hardware in the Loop (Vitis HIL) bridges simulation and hardware bring-up by enabling system-level verification on evaluation hardware directly from existing MATLAB® or Python™ test environments. Teams can reuse familiar testbenches, stimulus generation, reference models, and result-analysis workflows instead of rebuilding them for hardware validation. Rather than replacing simulation, Vitis HIL extends verification to real silicon when greater speed, scale, or hardware fidelity is required.

Software-Only Simulation for Heterogeneous Systems Can Be Complicated

Consider a representative heterogeneous DSP design: a polyphase channelizer implemented across AI Engine kernels and HLS-compiled programmable logic (PL) fabric on an AMD Versal VC1902 adaptive SoC. The design operates at an 8.75 GHz input sample rate and produces 16 sub-channel outputs. End-to-end verification with the AI Engine simulator or cycle-accurate RTL simulation requires millions of input samples to confirm convergence, sub-channel separation, and spectral fidelity across operating conditions. Processing these realistic data sets in software can take a long time, whereas the same workload runs much faster on the target hardware. As a result, exploring parameters such as cascade length, SSR factor, and twiddle precision through simulation alone becomes impractical.

Software simulation must model every pipeline stage, memory access, and inter-kernel data transfer, while the AI Engine array executes these operations in parallel at 1.25 GHz with deterministic, cycle-accurate timing. For the 16-channel polyphase channelizer described above, the clearest way to verify sub-band separation and phase alignment at the target sample rate is to run the design on silicon and observe the output directly.

Vitis HIL runs the design on physical silicon rather than emulating it or relying on a behavioral model. AI Engine kernels execute on the physical AI Engine array at the programmed clock frequency (typically 1.25 GHz) on the VCK190, while the PL fabric runs at its synthesized clock rates. Memory accesses use the actual programmable NoC and block RAM hierarchy. As a result, host-side observations capture real pipeline latency, fixed-point rounding, saturation behavior, and timing-dependent edge cases that software simulation may not reveal.

For complex DSP applications, hardware-speed execution makes measured performance directly representative of deployment. A polyphase filter bank using 400 AI Engine tiles at 1.25 GHz processes test vectors at hardware speed, so the latency and throughput measured with Vitis HIL are the values the deployed system will exhibit, not estimates derived from simulation cycle counts.

How It Works in 10 Steps

The Vitis HIL workflow has two phases. Phase 1 is a one-time build and board setup process. Phase 2 is the iterative test loop used as the design evolves. Engineers repeat Phase 1 only when the hardware architecture changes, not during routine test iterations.

Phase 1: Set Up

1. Configure a Vitis Subsystem with your AI Engine and programmable logic content
2. Generate a bootable SD card image using a single build command
3. Flash the image onto an SD card
4. Insert the SD card and power on the development board
5. Start the Vitis HIL server on the board

Phase 2: Test

Generate stimulus frames on the host using existing MATLAB® or Python™ scripts. Input data is wrapped in typed frame objects aligned to the Vitis HIL interface specification: no format conversion is needed.

1. Call the Vitis HIL run function with the input frame list. The client marshals the data over TCP, initiates a DMA transfer to the AI Engine PLIO interfaces, and waits for the output.
2. The AI Engine array and PL fabric execute the computation at the full silicon clock rate. Output data accumulates in DMA output buffers on the board.
3. The run call returns with processed output frames. A drain loop at the end of a test sequence flushes any data remaining in the hardware pipeline.

Apply reference comparison, spectral analysis, BER calculation, or any existing verification methodology directly in MATLAB® or Python™: no output format translation required.

Key Idea:
Existing MATLAB® or Python™ verification scripts can typically retain their stimulus-generation and result-analysis logic when adapted to the Vitis HIL frame and run APIs.

The round-trip path includes stimulus generation, Ethernet transmission, DMA transfer to the AI Engine PLIO interfaces, computation, DMA readback, Ethernet return, and result delivery. Total latency consists of kernel pipeline fill time plus approximately 2–5 µs of transport overhead. With large frames, four times the kernel frame size is a recommended starting point (DMA and TCP overhead becomes a negligible share of processing time, and sustained throughput approaches the memory bandwidth available to the Ethernet subsystem). After the test sequence, the getStats() API reports per-port DMA transfer counts and measured throughput for comparison with the design specification.

Designed for Both AI Engine and PL-Only Designs

Vitis HIL is built around the Vitis Subsystem (VSS), which packages AI Engine graphs and HLS PL kernels as a reusable IP block. Although the flow is designed primarily for heterogeneous systems, a VSS can also contain only HLS PL kernels. In that configuration, hil_gen generates a bitstream and the Vitis HIL server image that connect the PL kernels directly to the Ethernet-backed DMA infrastructure. The MATLAB® or Python™  APIs work the same way, allowing teams with traditional programmable logic DSP designs to use the same verification method and evaluation hardware without an AI Engine graph.

Vitis HIL provides a unified verification approach for designs ranging from PL-only fixed-point DSP implementations to full heterogeneous AI Engine and PL systems, with consistent tooling and host APIs across both.

The Hardware: Two Evaluation Kits, One Flow

Vitis HIL is fully supported on two AMD Versal™ evaluation kits. Both use the same 10-step workflow.

Supported Boards

VCK190 Evaluation Kit: Versal AI Core Series (VC1902). Purpose-built for aerospace & defense and low earth orbit (LEO) satellite DSP workloads where size, weight, and power (SWaP) constraints are critical: radar signal processing, sonar, SIGINT, and satellite payload applications.

VEK280 Evaluation Kit: Versal AI Edge Series (VE2802). Optimized for automotive and industrial edge applications: ADAS perception, sensor fusion, machine vision, and real-time signal processing before integration into a vehicle or industrial platform.

Both boards connect to the host through standard Ethernet and use the same MATLAB® or Python™  Vitis HIL APIs. Verification logic can therefore be reused across VCK190 and VEK280 targets, although the hardware design must be rebuilt for each selected device and board.

Who is Vitis HIL for?

Vitis HIL is designed for teams that need system-level validation beyond what software-only simulation can practically provide, including:

• Algorithm engineers validating throughput, latency, and numerical behavior before platform integration
• Signal processing engineers verifying waveform fidelity and deterministic latency for DSP workloads
• FPGA architects integrating AI Engine compute with PL-based routing, formatting, or protocol interfaces
• Verification engineers expanding test coverage with realistic data sets on real hardware
• System integrators validating end-to-end behavior across AI Engine and PL pipelines

Getting Started: Tools and Licensing

Vitis HIL is included with AMD Vitis 2026.1 and supports MATLAB® or Python™  host APIs for stimulus generation, result capture, and automated test execution. For detailed setup, supported data types, frame-size tuning, and optimization guidance, see the Vitis HIL User Guide (UG1865). For a practical walkthrough, Adam Taylor’s Hackster.io example demonstrates end-to-end verification of a polyphase channelizer using Vitis HIL on a VCK190 board.

Key Idea:
After the board is set up, routine test iterations can run from MATLAB® or Python™ without manual interaction with the hardware. When the design bitstream changes, the Vitis HIL workflow can script the update, restart the Vitis HIL server, and establish a new TCP connection, making the process suitable for automated and CI/CD environments.

Ready to validate on Real Silicon?

Learn more about Vitis HIL including a step-by-step walkthrough and how-to video.