Versal RF Series
Enables precise, wideband-spectrum observability with 18 GHz RF-ADCs and RF-DACs, providing up to 80 TOPS of DSP performance¹² in a SWaP-optimized design with commonly used DSP functions implemented as hard IP.
Advance Innovation in Your Design
Accelerated by the demands for AI, the need for increased data processing and faster connectivity makes efficiency crucial to minimizing the delay from data to insights. The AMD adaptive SoC and FPGA portfolio has a proven track record and will help you meet your product goals through unparalleled system-level efficiencies and supply chain resiliency. Choose AMD and unlock the future of adaptive computing solutions.
Unlock More System-Level Value
AMD Versal™ adaptive SoCs help you innovate faster with advanced IP, modern tools, and powerful hardware.
Ensure Supply Chain Reliability
The AMD global supply strategy delivers consistent products and short lead times.
Work with a Proven Industry Leader
AMD offers long-term stability, outstanding technical support, and a future-ready roadmap you can rely on.
Solutions
AMD devices provide flexible connectivity, optimized system performance and efficiency, security, and reliability. Transform your next design with innovative solutions built around the AMD adaptive compute portfolio.
Automotive ADAS Enablement
Enhance responsiveness, data processing, functional safety, and security in L2-L4 applications with AMD Versal AI Edge Series Gen 2 devices, which support a wide range of sensors, flexible real-time signal processing, and target 3X TOPS/W of AI inference performance vs. the 1st-generation Versal AI Edge Series.1
Addressing Wideband Spectrum Coverage
Modern RF applications require wide spectrum coverage, high sample rates with enhanced signal processing, and optimized SWaP. AMD Zynq™ UltraScale+™ RFSoC, Versal RF devices, and the Mercury Systems System-in-Package (SiP) cater to the full range of electromagnetic spectrum operations (EMSO).
Diagnostic Imaging Solutions
In healthcare, applications demand quality, reliability, security, safety, and product longevity. With Versal AI Edge Series Gen 2 devices, you can build the next wave of products without compromise, unlocking critical insights and delivering transformational outcomes.
Next-Level Broadcast AV Performance
From capturing content to enabling virtual production and creating live events, the enhanced video and graphics capabilities of Versal Prime Series Gen 2 devices enable Broadcast and Pro AV equipment suppliers to deliver even more compelling experiences.
Introducing the Security Features of AMD Spartan™ UltraScale+ and Versal Devices
Safeguarding your product against an evolving threat landscape is essential. Modern designs must be resilient in the face of side-channel attacks, bitstream tampering, firmware manipulation, glitch attacks, and supply chain vulnerabilities.
To learn how AMD FPGAs and adaptive SoCs offer a comprehensive defense strategy, read our white paper. To view AMD security comparisons versus the competition, visit the AMD Security Lounge.
Make the Easy Switch to AMD
AMD equips developers with the essential information, training, and support they need when migrating designs to AMD adaptive SoCs and FPGAs.
AMD Benefits
The AMD multi-faceted strategy embraces technological innovation, diversifies the supply chain, and enhances supply resiliency and agility.
- Efficiency
- NoC
- Thermal
- Connectivity
- Supply Chain Confidence
Unmatched Compute Efficiency
3x
RF Compute per Area
10x
Scalar Compute
3x
TOPS/Watt
The optimized hard IP in Versal adaptive SoCs results in higher system-level performance-per-watt.1 The AMD Versal RF Series offers 3X more compute per area compared to competing FPGAs.2 In addition, Versal AI Edge Series Gen 2 and Prime Series Gen 2 achieve 10X scalar compute and 3X TOPS/watt compared to previous generation architectures.1,4 Learn about the system-level benefits of the AMD Versal architecture and comparative performance to competing programmable-logic based devices in our white paper.
Programmable NoC for Efficient SoC Design
Build fast, efficient designs with the AMD Versal programmable NoC architecture.
58%
Lower Latency
60%
Fewer Resources
50%
Faster Development
Superior Design with Portfolio-Wide NoC
AMD Versal adaptive SoCs support a fully programmable network on chip (NoC), implemented as hard IP, across the entire portfolio. Hardware designers can benefit from up to 58% lower write latency, up to a 60% reduction in logic utilization, and up to a 50% reduction in development time versus competing FPGAs using a soft IP solution.5,6,7 Developers who are new to the Versal programmable NoC should check out the NoC related videos which are part of the Vivado for Versal video series.
Better Thermal Resistance
11x
Thermal Resistance
Innovative world-class AMD lidless packaging with stiffener ring technology reduces thermal resistance by up to 11X8 and helps lower power consumption. Reduce your product size and weight and support a wide ambient temperature range. With innovative packaging for thermal performance, AMD packaging tackles FPGA thermal demands in edge and high-performance deployments.
Faster Connectivity
2x
Faster Secure Data Transactions
AMD Versal adaptive SoCs provide the fastest LPDDR5 memory connectivity,9 up to 2X faster secure data transactions versus competing FPGAs,10 and enhanced host connectivity. AMD Versal Premium Series Gen 2 offers the industry’s first adaptive SoC with PCIe® Gen 6 and CXL® 3.1, scaling data transfer rates to 64 Gb/s to support memory- and data-intensive workloads.11
Maximize Supply Chain Confidence
AMD oversees the entire manufacturing supply chain, from raw materials to fabrication, and ensures that all suppliers adhere to high business continuity plan (BCP) standards. AMD delivers consistent product availability, predictable lead times, transparency, and reduced risk.
Together with our supply chain and industry partners, AMD embraces the opportunity to meet demand while driving social and environmental progress in the supply chain through supply chain responsibility. Discover the AMD approach to reducing global supply chain risk with agility and strategic foresight.
Portfolio
The AMD adaptive computing portfolio integrates security and reliability features to help ensure your designs will address the applications of tomorrow.
Case Studies
-
SERMA AI Avionics Solution Powered by AMD Versal™ Adaptive SoCs
The AI Avionics solution detects and identifies very thin objects at up to 100 meters using high-resolution camera.
September 09, 2025
-
Plum Optimizes AV-over-IP Delivery with AMD Adaptive SoCs
Powered by AMD Zynq™ adaptive SoCs, Plum’s Dante AV Ultra line delivers cutting-edge performance across global campuses
August 27, 2025
-
Canoga Perkins Delivers AI-Capable 5G Connectivity with AMD
Canoga Perkins achieves deterministic performance with ultra-low latency communication for industrial automation and enterprise AI with AMD FPGAs.
August 06, 2025
-
cellXica Delivers all-in-one Base Station Design with AMD
cellXica achieves connectivity with minimal footprint and power consumption for private 5G networks using AMD Zynq® UltraScale+™ RFSoCs
July 24, 2025
-
Osprey Video uses AMD Zynq™ Ultrascale+™ to develop video capture and streaming hardware
Osprey Video manufactures hardware for video capture and live streaming solutions where the AMD Zynq™ Ultrascale+™ enables full control and helps redu…
March 25, 2025
-
Magewell uses AMD FPGAs to develop USB video capture devices
Magewell is leveraging an AMD Artix™ UltraScale+™ FPGA to implement both the physical and digital layers of USB, eliminating the need for external con…
March 16, 2025
-
Solectrix Case Study
AMD Kria SOM helps Solectrix achieve fast, high-resolution image processing to enhance the safety of industrial machines.
March 04, 2025
-
Fujitsu uses AMD Zynq™ RFSoCs for power-efficient 5G radios
Fujitsu chose AMD Zynq™ RFSoC DFE devices to deliver cost-, capacity- and energy- efficient radios that meet various market requirements.
February 10, 2025
Resources
FAQs
The Versal programmable NoC is available across the entire Versal portfolio and is designed to provide a high-bandwidth path for both vertical and horizontal traffic across the entire device.
AMD lidless packages with stiffener ring, combined with AMD etch patterns enable the development of optimum thermal solutions.
AMD minimizes risk through partnerships, geographically diverse manufacturing, and assurance programs across the entire supply chain.
Yes. Developers should review the AMD security white paper and then visit the lounge to learn more about the AMD advantage.
Developers should review the AMD Design Conversion for FPGAs and SoCs Methodology Guide and also assess the level of difficulty of conversion on a module-by-module basis. Critical functions that may require factory support can be upleveled through local support channels.
Contact
Tell us how we can help you make the easy switch to AMD.
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Footnotes
- Tera operations per second (TOPS) / watt is based on AMD internal performance and power projections for the AIE-ML v2 compute tile architecture in the Versal AI Edge Series Gen 2 using the MX6 data type, compared to performance specifications and AMD Power Design Manager power results for the AIE-ML compute tile architecture featured in the first generation Versal AI Edge Series using the INT8 data type. Operating conditions: 1 GHz FMAX, 0.7V AIE operating voltage, 100°C junction temperature, typical process, 60% vector load, % activations = 0 < 10%. Actual performance will vary when final products are released in market. March 2024. (VER-023)
- Based on AMD testing in January 2025, using the AMD Power Design Manager 2024.2 to estimate the total power consumption of a single 18x12 AXI crossbar design with 24 transceivers, synthesized and implemented with Vivado Design Suite 2024.2, on the Versal Prime Series VM1402 device with the programmable NoC, versus the total power consumption of the same single design, synthesized and implemented with Altera Quartus 24.1, on the Altera Agilex 7 AGFB023 device with open-source AXI soft IP and estimated with Altera Quartus Power Thermal Calculator 24.2. Results assume a fixed junction temperature (ΘJC) of 100°C and maximum process leakage devices. Results will vary based on architecture, device, customer design specifications, system configuration, and other factors. (VER-090)
- Based on an AMD internal analysis comparing the theoretical processing capability (including hard IP, AI Engines, and DSP) of the Versal RF Series VR19xx devices versus the largest Altera Agilex 9 Direct RF-Series ARGW027 device. Results may vary based on device, design, configuration, and other factors. (VER-072)
- Based on the projected combined total DMIPs of the Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 processing systems when configured with 8 Arm Cortex-A78AE applications cores @2.2 GHz & 10 Arm Cortex-R52 real-time cores @1.05 GHz, compared to the published combined total DMIPs of the processing systems in the first generation Versal AI Edge Series and Versal Prime Series. Versal AI Edge Series Gen 2 and Prime Series Gen 2 operating conditions: Highest available speed grade, 0.88V PS operating voltage, split-mode operation, maximum supported operating frequency. First generation Versal AI Edge Series and Prime Series operating conditions: Highest available speed grade, 0.88V PS operating voltage, maximum supported operating frequency. Actual DMIPs performance will vary when final products are released in market. (VER-027)
- Based on AMD testing in January 2025, measuring the DDR read and write latency of a single multi-manager bridge design, implemented with AMD Vivado Design Suite 2024.1 and the AMD Versal Premium Series VP1202 device using the programmable NoC, versus the same design implemented with Altera Quartus 24.1, on the Altera Agilex 7 AGFB027 device using open-source AXI soft IP. Results will vary based on architecture, device, customer design specifications, system configuration, and other factors. (VER-086)
- Based on AMD testing in January 2025, comparing the post-implementation logic resource utilization of a single 18x12 AXI crossbar design with 24 transceivers, using the AMD Versal Prime Series VM1402 device with the programable NoC, implemented with AMD Vivado 2024.1 versus the Altera Agilex 7 AGFB023 device with open-source AXI soft IP, implemented with Altera Quartus 24.1. Results will vary based on architecture, device, customer design specifications, system configuration, and other factors. (VER-085)
- Based on AMD analysis in January 2025, summing the synthesis and implementation build times of a single 12x12 AXI crossbar design implemented with AMD Vivado 2024.2 on the AMD Versal Prime Series VM1402 device with the programmable NoC, versus the same design implemented with Altera Quartus 24.1, on the Altera Agilex AGFB023 device with open-source AXI soft IP. Results will vary based on architecture, device, customer design specifications, system configuration, and other factors. (VER-088)
- Based on AMD internal analysis in January 2025, using the AMD device and package thermal model to compare the JEDEC two-resistor thermal resistance Junction-to-Case (ΘJC) of the Versal Prime Series VM1802 device in a Versal VFVC1760 lidded package, versus the JEDEC two-resistor thermal resistance Junction-to-Case (ΘJC) of the same device in a Versal VSVD1760 lidless package with a stiffener ring. Results will vary based on architecture, device, customer design specifications, system configuration, and other factors. (VER-087)
- Based on AMD internal analysis of the memory bandwidth available with AMD Versal Premium Series Gen 2 devices [CXL 3.1 plus LPDDR5X memory] versus comparable competitive devices with LPDDR5 memory alone. Memory bandwidth will vary based on system configuration and other factors. (VER-059)
- Based on AMD internal analysis of Versal Premium Series Gen 2 devices with 400 Gb/s High-Speed Crypto Engines versus comparable competitive devices with 200 Gb/s crypto engines. Actual line rate speeds will vary based on system configuration and other factors. (VER-062)
- Based on an AMD internal analysis of the AMD Versal Premium Series Gen 2 device(s) with CXL 3.1 and PCIe 6.0 versus comparable competitive devices without CXL 3.1 and/or with PCIe Gen 4/5, as of July 2024. (VER-055)
- Tera operations per second (TOPS) for an AMD Versal RF Series device is the maximum number of operations per second that can be executed in an optimal scenario and may not be typical. TOPS will vary based on device, design, configuration, and other factors. (VER-084)
- Highest I/O-per-logic-cell is based on an AMD internal analysis of the product data sheet for AMD Spartan UltraScale+ SU10P FPGA and the published product data sheets for the comparable competitive FPGAs with a 28 nm and lower node-size, from Efinix, Intel, Lattice, and Microchip. Cost reduction per I/O is based on AMD list prices for the AMD Spartan UltraScale+ SU10P versus the AMD Spartan 7 7S50, as of February 2024, for designs requiring at least 200 GPIO. (SUS-011)
Footnotes
- Tera operations per second (TOPS) / watt is based on AMD internal performance and power projections for the AIE-ML v2 compute tile architecture in the Versal AI Edge Series Gen 2 using the MX6 data type, compared to performance specifications and AMD Power Design Manager power results for the AIE-ML compute tile architecture featured in the first generation Versal AI Edge Series using the INT8 data type. Operating conditions: 1 GHz FMAX, 0.7V AIE operating voltage, 100°C junction temperature, typical process, 60% vector load, % activations = 0 < 10%. Actual performance will vary when final products are released in market. March 2024. (VER-023)
- Based on AMD testing in January 2025, using the AMD Power Design Manager 2024.2 to estimate the total power consumption of a single 18x12 AXI crossbar design with 24 transceivers, synthesized and implemented with Vivado Design Suite 2024.2, on the Versal Prime Series VM1402 device with the programmable NoC, versus the total power consumption of the same single design, synthesized and implemented with Altera Quartus 24.1, on the Altera Agilex 7 AGFB023 device with open-source AXI soft IP and estimated with Altera Quartus Power Thermal Calculator 24.2. Results assume a fixed junction temperature (ΘJC) of 100°C and maximum process leakage devices. Results will vary based on architecture, device, customer design specifications, system configuration, and other factors. (VER-090)
- Based on an AMD internal analysis comparing the theoretical processing capability (including hard IP, AI Engines, and DSP) of the Versal RF Series VR19xx devices versus the largest Altera Agilex 9 Direct RF-Series ARGW027 device. Results may vary based on device, design, configuration, and other factors. (VER-072)
- Based on the projected combined total DMIPs of the Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 processing systems when configured with 8 Arm Cortex-A78AE applications cores @2.2 GHz & 10 Arm Cortex-R52 real-time cores @1.05 GHz, compared to the published combined total DMIPs of the processing systems in the first generation Versal AI Edge Series and Versal Prime Series. Versal AI Edge Series Gen 2 and Prime Series Gen 2 operating conditions: Highest available speed grade, 0.88V PS operating voltage, split-mode operation, maximum supported operating frequency. First generation Versal AI Edge Series and Prime Series operating conditions: Highest available speed grade, 0.88V PS operating voltage, maximum supported operating frequency. Actual DMIPs performance will vary when final products are released in market. (VER-027)
- Based on AMD testing in January 2025, measuring the DDR read and write latency of a single multi-manager bridge design, implemented with AMD Vivado Design Suite 2024.1 and the AMD Versal Premium Series VP1202 device using the programmable NoC, versus the same design implemented with Altera Quartus 24.1, on the Altera Agilex 7 AGFB027 device using open-source AXI soft IP. Results will vary based on architecture, device, customer design specifications, system configuration, and other factors. (VER-086)
- Based on AMD testing in January 2025, comparing the post-implementation logic resource utilization of a single 18x12 AXI crossbar design with 24 transceivers, using the AMD Versal Prime Series VM1402 device with the programable NoC, implemented with AMD Vivado 2024.1 versus the Altera Agilex 7 AGFB023 device with open-source AXI soft IP, implemented with Altera Quartus 24.1. Results will vary based on architecture, device, customer design specifications, system configuration, and other factors. (VER-085)
- Based on AMD analysis in January 2025, summing the synthesis and implementation build times of a single 12x12 AXI crossbar design implemented with AMD Vivado 2024.2 on the AMD Versal Prime Series VM1402 device with the programmable NoC, versus the same design implemented with Altera Quartus 24.1, on the Altera Agilex AGFB023 device with open-source AXI soft IP. Results will vary based on architecture, device, customer design specifications, system configuration, and other factors. (VER-088)
- Based on AMD internal analysis in January 2025, using the AMD device and package thermal model to compare the JEDEC two-resistor thermal resistance Junction-to-Case (ΘJC) of the Versal Prime Series VM1802 device in a Versal VFVC1760 lidded package, versus the JEDEC two-resistor thermal resistance Junction-to-Case (ΘJC) of the same device in a Versal VSVD1760 lidless package with a stiffener ring. Results will vary based on architecture, device, customer design specifications, system configuration, and other factors. (VER-087)
- Based on AMD internal analysis of the memory bandwidth available with AMD Versal Premium Series Gen 2 devices [CXL 3.1 plus LPDDR5X memory] versus comparable competitive devices with LPDDR5 memory alone. Memory bandwidth will vary based on system configuration and other factors. (VER-059)
- Based on AMD internal analysis of Versal Premium Series Gen 2 devices with 400 Gb/s High-Speed Crypto Engines versus comparable competitive devices with 200 Gb/s crypto engines. Actual line rate speeds will vary based on system configuration and other factors. (VER-062)
- Based on an AMD internal analysis of the AMD Versal Premium Series Gen 2 device(s) with CXL 3.1 and PCIe 6.0 versus comparable competitive devices without CXL 3.1 and/or with PCIe Gen 4/5, as of July 2024. (VER-055)
- Tera operations per second (TOPS) for an AMD Versal RF Series device is the maximum number of operations per second that can be executed in an optimal scenario and may not be typical. TOPS will vary based on device, design, configuration, and other factors. (VER-084)
- Highest I/O-per-logic-cell is based on an AMD internal analysis of the product data sheet for AMD Spartan UltraScale+ SU10P FPGA and the published product data sheets for the comparable competitive FPGAs with a 28 nm and lower node-size, from Efinix, Intel, Lattice, and Microchip. Cost reduction per I/O is based on AMD list prices for the AMD Spartan UltraScale+ SU10P versus the AMD Spartan 7 7S50, as of February 2024, for designs requiring at least 200 GPIO. (SUS-011)