MicroBlaze V Processor Quick Start Guide
This Quick Start Guide will walk you through creating a basic AMD MicroBlaze V processor system using processor preset designs.
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Overview
The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD adaptive SoCs and FPGAs. The MicroBlaze V processor is based on the RISC-V instruction set architecture (ISA). It allows developers to leverage the open-source RISC-V software ecosystem, is hardware compatible with the classic MicroBlaze processor, and is fully integrated in the AMD Vivado™ and Vitis™ tools design flow. The AMD MicroBlaze V processor is designed to be highly modular with a configurable architecture suitable for embedded systems applications.
Developers can target the MicroBlaze V processor to any AMD adaptive SoC or FPGA device supported by the Vivado Design Suite at no extra cost.
RISC-V is an open-source standard instruction set architecture (ISA) that is managed by the non-profit RISC-V Foundation. AMD has been a member since 2020.
Key Capabilities
Based on RISC-V
Open-Source ISA
- Backed by a comprehensive ecosystem of software and solutions throughout the industry
- Enables easy hardware migration for existing MicroBlaze processor designs and software portability for RISC-V designs
- Configurable ISA support for RV32I and RV64I Base Integer Instruction Set with optional:
- Multiplication and division ("M" extension)
- Atomic instructions ("A" extension)
- Floating-point ("F" extension)
- Code compression ("C" extension)
- Bit manipulation (:B:, "ZBa", "ZBB", "ZBc", "ZBs" extensions)
- Offers code compression to significantly reduce code size and save design memory
Efficient Architecture at its Core
- Offers multiple selectable preset configurations for different applications from microcontroller to application processor
- Provides four pipeline options to optimize area and/or performance
- Incorporates optional safety measures like dual-core lockstep and triple modular redundancy (TMR) for safety-critical systems
High Degree of Design Flexibility
- Offers a fully integrated design flow in the Vivado design suite and Vitis software tools
- Compatible with all AMD adaptive SoCs and FPGAs supported in the Vivado design tools
- Offers a user-friendly experience with either a graphic user interface (GUI) or command line interface (CLI)
- Reduces system component count and shortens development time with a wide range of optimized IP available to deploy an integrated MicroBlaze V processor subsystem in the programable logic
Leverage the tried, tested, and trusted MicroBlaze™ processor from AMD. With its versatile uses and consistent performance, it's a dependable choice for numerous applications.
Processor Details
Key Drag and Drop Peripherals
General Purpose
- Multichannel DMA
- Streaming FIFO
- Timer / Watchdog
- Mutex / Mailbox
I/O
- UART
- USB 2.0
- SPI
- GPIO
- PWM
Video
- HDMI Camera/Display Interface
- MIPI-CSI, MIPI-DSI
- Video DMA
Memory
- DDR
- Quad SPI
- SDRAM
Networking
- Ethernet Subsystem
- Controller Area Network
Example Design Configurations
- MicroBlaze V Microcontroller
- MicroBlaze V with Memory Protection Unit
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MicroBlaze V Microcontroller
- 32-bit Processor Core (RV32IMAFC)
- JTAG Debug Interface
- Tightly Coupled Local Memory
- SPI controller
- I2C Controller
- UART
- Interrupt Controller
- Timer
- GPIO
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MicroBlaze V with Memory Protection Unit
- All Microcontroller Preset Blocks
- Instruction Cache
- Memory Protection Unit
- Data Cache
- Memory Controller
Support & Resources
Get Started
The MicroBlaze™ V Processor is integrated into AMD Vivado™ and Vitis™ providing users a familiar design flow. Watch the webinar and learn all about MicroBlaze V and its benefits.
Footnotes
1. Microcontroller configuration available in Production; AMD MicroBlaze V with RV64I and Memory Protection Unit are in Early Access; AMD MicroBlaze V with Memory Management Unit is on the roadmap.
Footnotes
1. Microcontroller configuration available in Production; AMD MicroBlaze V with RV64I and Memory Protection Unit are in Early Access; AMD MicroBlaze V with Memory Management Unit is on the roadmap.