AMD Spartan UltraScale+ FPGA
- Industry’s highest I/O-to-logic-cell ratio in FPGAs built on 28 nm and smaller process technology3
- Up to 30% lower total power consumption vs. the previous generation9
Cost-Efficient Solutions Start with Innovative Silicon and Superior Tools
Greater value. Faster time to market. Lower total solution cost.1
Total solution cost involves more than just silicon. Truly cost-optimized FPGA solutions consider fabric efficiency, packaging characteristics, design tool costs and usability, IP licensing and integration, development effort, and more.
We start with state-of-the-art silicon to meet your performance and power specifications. Our proven, push-button tools simplify the design flow and provide flexibility to get your product to market quickly. Supported by the industry’s largest ecosystem of partners and IP, AMD helps you stay ahead of competition.2
See how AMD does it better – from start to finish.
Solutions
Accelerate your innovation from vehicle to factory to cloud.
Build solutions faster with the industry’s largest development ecosystem.2
Achieve real-world impact with a trusted partner while lowering total solution cost.
Automotive
Enhance night vision, pedestrian detection, and automatic emergency braking (AEB) with energy-efficient, real-time image processing for long-wave infrared (LWIR) cameras. Simplify thermal management and speed up your market entry with an extensive automotive IP ecosystem from AMD, including partners like Stradvision, Xylon, and Makarena.
Automotive Night Vision Cameras with AMD Artix™ UltraScale+™ XA FPGAs
See how power efficiency, compact form factors, and crucial safety and security features enable faster image sensor processing and real-time responsiveness for LWIR cameras.
Machine Vision
AMD FPGAs deliver compact, energy-efficient real-time image processing and simplified thermal management. Access open-source libraries, 250+ free AMD Vivado™ IP cores, 700+ Vitis™ functions, and free MicroBlaze™ V processors to rapidly develop and deploy AI-powered machine vision solutions.
Differentiate Machine Vision Cameras with AMD FPGA Advantages
The AMD FPGA and adaptive SoC portfolio delivers low-cost solutions, while supporting the latest sensor and output interfaces needed for today’s fast-paced production lines.
Industrial Automation
Boost productivity with power-efficient FPGA and SoC solutions for robotics and factory automation. Maximize edge intelligence for autonomous robots, simplify thermal management, and accelerate development with AMD Time Sensitive Networking IP.
Industrial Automation Field Equipment with AMD Cost-Optimized Devices
See how AMD enables efficient actuator control, high-speed data acquisition, and low-power image processing.
Data Center
Scale intelligent server and data center baseboard management controller (BMC) solutions with AMD cost-optimized FPGAs and adaptive SoCs, offering industry-leading I/O-per-logic ratio3 for efficient rack use and improved TCO. Accelerate BMC integration with the AMD robust ecosystem and AMD EPYC™ Processor Reference Design.
AMD CPU and FPGA Integration for Server I/O
With built-in security for PQC algorithms, OCP-compliant (DC-SCM 2.1) interoperability, and rapid development using the AMD Vivado Design Suite, these solutions enable fast, secure, and scalable BMC deployment for intelligent data centers.
Broadcast & Pro AV
AMD cost-optimized FPGAs and adaptive SoCs deliver high-bandwidth, low-power solutions for Pro AV, enabling seamless PCIe® Gen4 video capture, processing, and 4K playout in compact designs. Advanced I/O, integrated memory controllers, and broad video interface support make them ideal for next-gen professional audio-visual systems.
Advancing Broadcast & Pro AV with AMD Spartan™ UltraScale+ FPGAs
Equipped with high-speed 16.3 Gb/s transceivers, built-in external memory controllers, and PCIe Gen4 interfacing, AMD Spartan UltraScale+ FPGAs enable professional AV and broadcast applications from AV-over-IP network bridges, video converters, and PCIe ingest, playout, and processing cards.
How AMD Does it Better
- Silicon
- Design Tools
- System Integration
Silicon
Do more with Spartan UltraScale+ FPGAs. Cutting-edge fabric architecture, top-of-the-line peripherals, and superior thermal packaging4 provide industry-leading performance5 for your cost-sensitive applications. Find the device that fits your needs today and for the future.
40%
More Efficient Designs
40% better average utilization with LUT6 vs. competing LUT4 architecture6 because efficient designs start with efficient architecture!
1.8x
More Hertz
1.8X higher FMAX on average vs. the competition using the same 16 nm process node at the highest speed grades.5
46%
Fewer Watts
Up to 46% lower total power consumption with the Spartan UltraScale+ FPGA’s LUT6 architecture, and advanced packaging for high-performance designs vs. the competition’s LUT4 architecture.7
Design Tools
Save valuable time. Eliminate unnecessary iterations and avoid downloading additional tools. The Vivado Design Suite is a single streamlined development tool for AMD cost-optimized FPGAs. It is fully integrated across the design flow, including all capabilities needed to go from RTL design to implementation and debug.
100%
Pass Rate
Superior Timing Closure8
Experience out-of-the-box success without having to fight timing closure. Design efficiently while maximizing productivity with the Vivado Design Suite.
Unified Flow for Fewer Iterations
The Vivado Design Suite provides a fully integrated solution from simulation to debug, eliminating the need for costly third-party tools and reducing time to market.
500+
Developer-Driven, Feature-Rich
The Vivado Design Suite offers a robust, free IP catalog of more than 500 functions and IP for a wide range of applications.
System Integration
AMD provides leading building blocks for you to secure, certify, and integrate system components—quickly and easily.
Secure Systems Start with Secure Boot
Secure your system with CNSA 2.0 PQC-compliant secure boot and multi-level protection from AMD:
- RSA-2048
- NIST-certified AES-GCM post-quantum cryptography
- Physical Unclonable Function (PUF) and True Random Number Generator (TRNG)
- Anti-tamper capabilities
Functional Safety
Accelerate market entry for silicon and software with TUV SUD certified AMD safety design flows including:
- Design and verification tools certified for use in functional safety applications
- Certified compiler tools
- Certified functional safety design methodologies and IP cores
SoC Integration
AMD adaptive SoCs integrate multiple functions into a single chip, boosting performance, reducing latency, and enhancing security.
- Integrated Arm® Cortex® processors, Mali™ GPUs, video encoding, programmable logic
- Reduced attack surface for improved security
Portfolio
Adaptable Solutions for Cost-Sensitive Applications
AMD offers a broad portfolio of adaptable solutions for cost-sensitive applications. AMD UltraScale+ and 7 Series FPGAs & adaptive SoCs are based on LUT6 architecture, designed to maximize performance while remaining cost-optimized for the price-sensitive customer.
Resources
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Get started with the AMD Cost-Optimized Portfolio.
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Footnotes
The information contained herein is for informational purposes only and is subject to change without notice. No technology or product can be completely secure. GD-122.
- The AMD Cost-Optimized Portfolio (“COP”) is designed to offer a ‘lower cost solution’, based on AMD internal assumptions, estimates, and best approximations. This claim is representative of the AMD COP, for informational purposes only. AMD recommends customers base purchase decisions on actual testing. See here for additional information. (COP-004)
- Based on AMD internal analysis as of June 2025 of published ecosystem partners of FPGA vendors, including factors such as market share, development tools, community engagement, and industry recognition. (COP-005)
- Highest I/O per logic cell is based on an AMD internal analysis of the product data sheet for AMD Spartan UltraScale+ SU10P FPGA and the published data sheets for the comparable competitive FPGAs with a 28 nm and lower node-size, from Efinix, Intel, Lattice, and Microchip. Cost reduction per I/O is based on AMD list prices for the AMD Spartan UltraScale+ SU10P versus Spartan 7 7550 FPGA, as of February 2024, for designs requiring at least 200 GPIO. (SUS-011)
- Based on July 2024 AMD analysis of published data sheets using standard JESD51 definition for θJa versus equivalent Lattice packages. Stated results are provisional and will vary based on architecture, package size, speed grade, device, design, configuration, and other factors. (COP-002)
- Based on AMD analysis in July 2024, calculating FMAX ratios averaged over 30 open-core designs for (16 nm) AMD Artix UltraScale+ AU7P FPGA, compared to the (16 nm) Lattice Avant E70 FPGA, at the respective highest speed grades. Results will vary based on architecture, device, speed grade, package size, design, configuration, and other factors. (AUS-010)
- Based on AMD testing in July 2024, measuring the utilization scores of the LUT6 architecture-based AMD Artix 7 A100T (28 nm) and Artix UltraScale+ AU7P (16 nm) versus the LUT4 architecture-based Lattice Nexus MachXO5 25 (28 nm) and Lattice Avant E70 (16 nm) devices, measured on AMD Vivado 2024.1 and Lattice Radiant 2024.1, respectively, at various speed grades, averaged over 30 open-core designs. Results will vary based on architecture, device, speed grade, package size, design, configuration, and other factors. (COP-001)
- Based on AMD testing in July 2024, performed in AMD Power Estimation Tools (XPE_2019_1_2 for 28 nm and PDM_2024.1 for 16 nm), and Lattice Radiant Power Estimation Tool 2024.1, to measure the power consumption of the AMD Spartan UltraScale+ SU35P, SU50P, and SU100P FPGAs versus Lattice MachXO5-NX-25, CertusPro-NX50, and MachXO5-NX-100T FPGAs at HP speed grade. Total Power results include fabric power and HDIO only. Stated results assume a normalized max ambient temperature of 100°C and a 40% utilization advantage for LUT6, when selecting competitive devices for comparison. Results are subject to change when products are released in market and will vary based on architecture, package size, speed grade, device, design, configuration, and other factors. (SUS-014)
- Based on AMD place-and-route testing in September 2024, using 26 open-core designs compiled with AMD Vivado 2024.1 and Lattice Radiant Software 2024.1 in default mode, with the AMD Artix UltraScale+ AU10P device versus Lattice Mach LFMXO5 device @ 150 MHz FMAX target; and AMD Kintex UltraScale+ KU5P device versus Lattice Avant E70 device @ 200 MHz FMAX target. P&R performance will vary based on device, design, configuration, and other factors. (VIV-011)
- Projection is based on AMD labs internal analysis in January 2024, using total power calculation (static plus dynamic power) based on the difference in logic cell count of an AMD Artix UltraScale+ AU7P FPGA, to estimate the power of a 16 nm AMD Spartan UltraScale+ SU35P FPGA versus a 28 nm AMD Artix 7 7A35T FPGA, using Xilinx Power Estimator (XPE) tool version 2023.1.2. Total power estimates and projections will vary when products are released in market and based on design, configuration, usage, and other factors. (SUS-003)
Footnotes
The information contained herein is for informational purposes only and is subject to change without notice. No technology or product can be completely secure. GD-122.
- The AMD Cost-Optimized Portfolio (“COP”) is designed to offer a ‘lower cost solution’, based on AMD internal assumptions, estimates, and best approximations. This claim is representative of the AMD COP, for informational purposes only. AMD recommends customers base purchase decisions on actual testing. See here for additional information. (COP-004)
- Based on AMD internal analysis as of June 2025 of published ecosystem partners of FPGA vendors, including factors such as market share, development tools, community engagement, and industry recognition. (COP-005)
- Highest I/O per logic cell is based on an AMD internal analysis of the product data sheet for AMD Spartan UltraScale+ SU10P FPGA and the published data sheets for the comparable competitive FPGAs with a 28 nm and lower node-size, from Efinix, Intel, Lattice, and Microchip. Cost reduction per I/O is based on AMD list prices for the AMD Spartan UltraScale+ SU10P versus Spartan 7 7550 FPGA, as of February 2024, for designs requiring at least 200 GPIO. (SUS-011)
- Based on July 2024 AMD analysis of published data sheets using standard JESD51 definition for θJa versus equivalent Lattice packages. Stated results are provisional and will vary based on architecture, package size, speed grade, device, design, configuration, and other factors. (COP-002)
- Based on AMD analysis in July 2024, calculating FMAX ratios averaged over 30 open-core designs for (16 nm) AMD Artix UltraScale+ AU7P FPGA, compared to the (16 nm) Lattice Avant E70 FPGA, at the respective highest speed grades. Results will vary based on architecture, device, speed grade, package size, design, configuration, and other factors. (AUS-010)
- Based on AMD testing in July 2024, measuring the utilization scores of the LUT6 architecture-based AMD Artix 7 A100T (28 nm) and Artix UltraScale+ AU7P (16 nm) versus the LUT4 architecture-based Lattice Nexus MachXO5 25 (28 nm) and Lattice Avant E70 (16 nm) devices, measured on AMD Vivado 2024.1 and Lattice Radiant 2024.1, respectively, at various speed grades, averaged over 30 open-core designs. Results will vary based on architecture, device, speed grade, package size, design, configuration, and other factors. (COP-001)
- Based on AMD testing in July 2024, performed in AMD Power Estimation Tools (XPE_2019_1_2 for 28 nm and PDM_2024.1 for 16 nm), and Lattice Radiant Power Estimation Tool 2024.1, to measure the power consumption of the AMD Spartan UltraScale+ SU35P, SU50P, and SU100P FPGAs versus Lattice MachXO5-NX-25, CertusPro-NX50, and MachXO5-NX-100T FPGAs at HP speed grade. Total Power results include fabric power and HDIO only. Stated results assume a normalized max ambient temperature of 100°C and a 40% utilization advantage for LUT6, when selecting competitive devices for comparison. Results are subject to change when products are released in market and will vary based on architecture, package size, speed grade, device, design, configuration, and other factors. (SUS-014)
- Based on AMD place-and-route testing in September 2024, using 26 open-core designs compiled with AMD Vivado 2024.1 and Lattice Radiant Software 2024.1 in default mode, with the AMD Artix UltraScale+ AU10P device versus Lattice Mach LFMXO5 device @ 150 MHz FMAX target; and AMD Kintex UltraScale+ KU5P device versus Lattice Avant E70 device @ 200 MHz FMAX target. P&R performance will vary based on device, design, configuration, and other factors. (VIV-011)
- Projection is based on AMD labs internal analysis in January 2024, using total power calculation (static plus dynamic power) based on the difference in logic cell count of an AMD Artix UltraScale+ AU7P FPGA, to estimate the power of a 16 nm AMD Spartan UltraScale+ SU35P FPGA versus a 28 nm AMD Artix 7 7A35T FPGA, using Xilinx Power Estimator (XPE) tool version 2023.1.2. Total power estimates and projections will vary when products are released in market and based on design, configuration, usage, and other factors. (SUS-003)