AMD Vivado™ Design Suite 2026.1 Software Release Highlights:

New subscription-based licensing model with more flexible licensing options

NoC and QoR enhancements for AMD Versal™ ​devices

  • Multi-top NoC simulation, new text-based report and logical NoC viewer
  • QoR enhancements with retiming updates, XPM memory optimization, and mixed RAM directive

DFX + Segmented Configuration support within PL

  •  Enabling the Dynamic Function eXchange (DFX) flow within the programmable logic for 2nd generation Versal devices with Segmented Configuration as the default flow​

Advanced Configuration Editor (ACE)

  • A stand-alone, design-aware utility that helps define and manage the subsystem composed of processors, memory, and peripherals
  • Applies safety and security requirements to the subsystem

Ease-of-Use Enhancements

  • Enhanced HDL support​
  • Processing System Wizard improvements
  • GUI improvements​

AMD Vivado™ Design Suite 2026.1 What's New by Category

Expand the sections below to learn more about the new features and enhancements in Vivado 2026.1.

New devices supported:

  • AMD Versal™ AI Edge Series Gen 2: XC2VE3358, XC2VE3504, XC2VE3558, XC2VE3804, and XC2VE3858 with new packages and speed grades
  • AMD Versal Prime Series Gen 2: XC2VM3558 and XC2VM3858 with new packages and speed grades
  • AMD Versal RF: XCVR1602 and XCVR1652
  • AMD Spartan™ UltraScale+™: XCSU45P, XCSU60P and XCSU200P

  • Multi-top NoC simulation: New parallel top-level instance automatically created for NoC simulation, allowing a cleaner solution that does not disrupt the user’s top-level simulation structure
  • New text-based NoC report: A unified report for all NoC elements in the design to better understand QoS requirements ​
  • Logical NoC viewer: A new and separate graphical viewer that displays all NoC masters (NMUs) and NoC slaves (NSUs), including the virtual NoC interfaces / INI instances, across the entire design

  • Versal QoR enhancements with retiming updates, XPM memory optimization, and mixed RAM directive

  • A stand-alone, design-aware utility that helps define and manage the subsystem composed of processors, memory, and peripherals
  • Applies safety and security requirements to the subsystem

  • Processing System Wizard improvements for Versal devices
    • Support for MIO voltage configuration per I/O bank and cluster-aware power analysis
    • Support for security and device integrity features through the Processing System Wizard
    • Ability to update the PLM without requiring a full system reboot
    • Addition of interactive block diagram support for Versal RF devices

  • Enabling the Dynamic Function eXchange (DFX) flow within the programmable logic for 2nd generation Versal devices with Segmented Configuration as the default flow
  • Updated lock_design level routing command to lock the static portion of the DFX design after implementation from initial configuration 

  • Enhanced HDL support with new constructs from VHDL 2008 and VHDL 2019 are supported in synthesis as well as simulation
  • New look and feel for Vivado IDE, making the interface more intuitive and visually appealing
  • Board-infrastructure-based filtering to view the list of example designs

AMD Vivado™ 2025.2 Software Release Highlights:

Versal QoR Enhancements

  • Reduced physical optimization (PhysOpt) compile time
  • Global or module-level optimization control with updates to retiming
  • BUFG_FABRIC replication per-SLR and per-VNoC column for high-fanout nets ​

SystemVerilog Interfaces Support

  • Simplified AXI connections between SV instances and automatic wrapper creation and management for all AMD IP and BDs

Ease-of-Use Enhancements

  • New and improved reporting on SLR crossings for better QoR analysis
  • New ECO legalizer for DRC checks and support for timing-driven mode in ECO placer
  • New options to enable Segmented Configuration in the Vivado Hardware Manager for direct programming and indirect (flash) programming flows​

Use of NoC XPMs inside Block Design Using Module Referencing

  •  Support for adding an RTL with NoC XPMs in the top-level block design (BD) using module referencing

Vivado 2025.2 Software What's New by Category

Expand the sections below to learn more about the new features and enhancements in Vivado 2025.2 software.

  • New devices supported:  
    • Versal AI Edge Series Gen 2: XC2VE3504, XC2VE3558, XC2VE3804, XC2VE3858 ​
    • Versal Prime Series Gen 2​: XC2VM3558, XC2VM3858 

  • Reduced physical optimization (PhysOpt) compile time
  • Global or module-level optimization control with updates to retiming
  • Support for adding an RTL with NoC XPMs in the top-level block design (BD) using module referencing
  • Simplified AXI connections between SV instances and automatic wrapper creation and management for all AMD IP and BDs
  • BUFG_FABRIC replication per-SLR and per-VNoC column for the high-fanout nets
  • Improved messaging on mutually exclusive pblock property settings

  • A new ultra-low-area mode supported for AXI Switch and AXI SmartConnect IP via STRATEGY parameter  
  • New block diagram and swim-lane views available in the PS Wizard IP for Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 

  • New look and feel for the IDE making the interface visually appealing with the modernized layout, introduction of new light and dark themes and revamped Welcome page.
  • New SLR crossing report and new options on SLR crossing added to the existing timing reports for better QoR analysis
  • New ECO legalizer for the DRC checks and support for timing-driven mode in the ECO placer
  • New options to enable Segmented Configuration in the Vivado Hardware Manager for direct programming and indirect (flash) programming flows

  • New switch “is_reconfigurable” added to the existing get_dfx_footprint command to find non-reconfigurable tiles
  • A new read only “IS_DFX” property on reconfigurable pblocks ​

  • Extended language support for the VHDL 2019 constructs for simulation, such as reference port elements in port declaration, regularize component declarations, attributes of enumerated types, range expressions -- 'range'record, 'range'value, infer subtype from initial value, function return subtype inferred from context, optional semicolon at the end of interface list.

AMD Vivado™ 2025.1 Software Release Highlights:

Unified Selective Device Installer for All Versal Devices

  • Reduces the Vivado download size significantly compared to previous versions
  • Enables users to select one or more devices, instead of an entire series while installing the Vivado Design Suite

Versal QoR Enhancements

  • Calibrated Deskew: Option to enable calibrated skew compensation to minimize local and global skews for Versal SSIT devices only ​​
  • Multi-phase NoC Support: Time-slice the QoS and bandwidth requirements to maximize the NoC performance

Flexible Boot of Processing System in Versal Devices​

  • Boot the processing system first and then dynamically load the PL on the fly
  • Public access for all production Versal devices​
  • Default flow for Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 devices

Continuing to Enable RTL Flows​

  • New AXI Switch IP: A fully customizable RTL-based IP that serves as a bridge between different AXI interface types and widths

Ease-of-Use Enhancements ​

  • Two dedicated “Clocking and Reset” and “Interrupt and AXI-4 Lite” views in the IP Integrator, providing more information
  • New Pblock planner; a one-stop shop, with everything related to creating a pblock ​
  • New addressing GUI for automatic grouping of the equivalent address spaces for Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 devices
  • GUI support for report_dfx_summary, which provides direct access to data specific to DFX for enhanced debugging ​

Vivado 2025.1 Software What's New by Category

Expand the sections below to learn more about the new features and enhancements in Vivado 2025.1 software.

  • Production-ready devices:
    • Spartan UltraScale+: XCSU10P, XCSU25P, XCSU35P 
       
  • In general access (GA) devices:
    • ​Versal AI Edge Series Gen 2: XC2VE3558, XC2VE3504, XC2VE3858, XC2VE3804 ​
    • Versal Prime Series Gen 2​: XC2VM3558, XC2VM3858 

  • Ability to boot the processing system first and dynamically load the PL on the fly, enabling fast bring-up of OS and diverse boot sequence flows
  • Option to enable calibrated skew compensation to minimize local and global skews for Versal SSIT devices only ​​
  • Time-slice the QoS and bandwidth requirements to maximize NoC performance
  • New Pblock planner; a one-stop shop, with everything related to creating a pblock
  • Improved Directive/Subdirective support for QoR gain​ by providing a Tcl script that automatically maps the default directives in the standard flow to the new directives/subdirectives in the Advanced Flow​

  • A fully customizable RTL-based AXI Switch IP which serves as a bridge between different AXI interface types and widths
  • Two dedicated “Clocking and Reset” and “Interrupt and AXI-4 Lite” views in the IP Integrator, providing more information
  • New addressing GUI for automatic grouping of the equivalent address spaces for Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 devices

  • GUI support for report_dfx_summary, which provides direct access to data specific to DFX for enhanced debugging ​

  • Added support for the VHDL 2019 constructs for simulation, such as Conditional expressions, Conditional return, Empty record, and Mode view for interfaces and code coverage exclusion etc. ​

AMD Vivado™ 2024.2 Release Highlights:

Fast Place and Route for All Versal™ Devices

  • Advanced Flow with automatic partition-based placement and parallel place and route (P&R)
  • Reduces congestion and improves routability for fast design closure
  • Default flow for all Versal devices

Enabling Top-Level RTL Flows

  • Enables usage of Versal programmable network on chip (NoC) and transceivers from the top-level RTL.

Segmented Configuration for Fast Boot of Processing System (PS) in Versal Devices

  • PS is booted first, with deferred configuration of programmable logic (PL)
  • Fast bring-up of OS with DDR
  • Meeting diverse boot sequence requirements

Ease-of-Use Features

  • New real-time preset for the AMD MicroBlaze™ V processor
  • Inline HDL of utility IP allows faster IP load and configuration
  • Enhanced DFX Floorplan Visualization and DFX Summary Report
  • New utility for PDI debug (decode and analyze boot configuration errors)
  • GUI enhancements for Pblocks during floorplanning
  • Renaming of kernel-shared library for Xilinx Simulator Interface (XSI)

AMD Vivado 2024.2 includes major enhancements for designing with AMD Versal™adaptive SoCs. Learn More.

Vivado 2024.2 What's New by Category

Expand the sections below to learn more about the new features and enhancements in Vivado 2024.2.

  • New Advanced Flow for all Versal devices, enabling partition-based placement and parallel P&R to reduce congestion and routability for fast design closure
  • Ability to boot processing subsystem first while deferring configuration of programmable logic, enabling fast bring-up of OS and diverse boot sequence flows
  • GUI enhancements for Pblocks during floorplanning—including tool tips, “snap-mode” placement, and fast access to property settings

  • Support for real-time preset for MicroBlaze V IP
  • Ability to configure key components of hard IP in Versal devices such as CIPS, NoC, and transceivers from top-level RTL
  • Inline HDL of utility IP for faster IP load and configuration

  • Enhanced DFX floorplan visualization to facilitate implementation
  • DFX summary report of key metrics to guide users for optimization 

  • New utility for PDI debug (decode and analyze boot configuration errors)
  • Renaming of kernel shared library for Xilinx Simulator Interface (XSI)

Vivado 2024.1 Release Highlights

General Access of MicroBlaze™ V soft processor (based on RISC V Open-Source ISA)

QoR (FMAX) Enhancements for Versal™ Devices

  • Optimized clocking and P&R across SLR boundaries (for multi-SLR Versal devices)​
  • User-controlled retiming during physical optimization​
  • User-controlled clock tree selection for clock skew minimization​

Dynamic Function eXchange (DFX) Enhancements​

  • Enhanced reporting of DFX designs to assist with design closure​
  • Add support for tandem configuration and DFX targeting Versal SSIT devices to meet PCIe® timing requirements​

Power Design Manager​

  • Added Zynq™ RFSoC family support​
  • Built-in graphs for what-if analysis and visualization of power categories​
  • Ability to export PDM content to spreadsheet for fast information sharing

Vivado What's New by Category

Expand the sections below to learn more about the new features and enhancements in Vivado 2024.1.

Synthesis & Implementation

  • Optimized clocking and P&R for designs spanning SLR boundaries (multi-SLR Versal devices)
  • User-controlled retiming during physical optimization
  • User-controlled clock tree selection for clock skew minimization
  • Enhanced clock placement and partitioning for designs with many low fanout clocks

IP Integrator

  • More consistent project recreation from TCL scripts to help with revision control of IPI-based designs
  • General access of MicroBlaze V soft processor (based on RISC V Open-Source ISA)

Dynamic Function eXchange

  • Enhanced reporting of DFX designs to assist with timing closure
  • Tandem configuration for meeting PCIe® timing requirements (Versal Premium and Versal HBM Series)
  • NoC clock gating for power reduction

What’s New - 2023.2 Release Highlights

Meeting Fmax targets​

  • Increase performance of designs in Versal Premium and Versal HBM devices with automatic place & route of SLR crossings
  • Faster device image generation with multi-threaded support

Ease of use enhancements in IPI, DFX, Debug and Simulation​​

  • New GUI window added for address path visualization from source and sink for Versal devices in IPI
  • Manually Assigned Address Locking Capability in BDs (IPI)
  • Improved visualization for DFX floorplans in Versal devices
  • Added support for Tandem+DFX in the same design for Versal Monolithic devices
  • Expanded support for Tandem Configuration for Queue DMA IP in UltraScale+™ devices
  • Vivado Simulator VCD support for SystemC users

Vivado ML What's New by Category

Expand the sections below to learn more about the new features and enhancements in Vivado™ ML 2023.2

Device Support

Devices that are production-ready:

  • Versal HBM: XCVH1742 and XCVH1782
  • Versal Premium: XQVP1502, XQVP1202 and XQVP1402

Synthesis & Implementation

  • Increase performance of designs in Versal Premium and Versal HBM devices with automatic place & route of SLR crossings
  • Faster device image generation with multi-threaded support

IP Integrator

  • New GUI window added for address path visualization from source and sink for Versal devices in IPI
  • Manually Assigned Address Locking Capability in BDs (IPI)

Dynamic Function eXchange

  • Improved visualization for DFX floorplans in Versal devices
  • Added support for Tandem+DFX in the same design for Versal Monolithic devices
  • Expanded support for Tandem Configuration for Queue DMA IP in UltraScale+ devices

Debug & Simulation

  • Vivado XSIM VCD support for SystemC users
  • Adding STAPL file support for UltraScale+ devices
  • Third-party simulator support updates

What's New in 2023.1 Key Highlights

  • Average QoR Improvement of 8% for Versal™ adaptive SoCs and 13% for UltraScale+ FPGAs using Intelligent Design Runs*
  • Power Design Manager (PDM) now a part of Unified Installer
  • Added support for Versal HBM devices in PDM
  • Extending multithreading support for bitstream generation for Versal devices
  • Enhancements in Report QoR Assessment (RQA)

Vivado ML What's New by Category

Expand the sections below to learn more about the new features and enhancements in Vivado™ ML 2023.1.

Devices that are production-ready

  • Versal AI Core Devices: XQVC1702 

  • Code Coverage Support
  • Updated simulation tools for 3rd party tools
  • Enhanced support for export simulation flow 

  • Bitstream generation via multithreading – Extending support for Versal
  • Flexible MARK_DEBUG Processing during PnR
  • New Post-Placement Physical Optimizations
  • VHDL-2019 Support 

  • Intelligent Design Run (IDR) improvements – For Versal and UltraScale+ Designs
  • Report QoR Assessment (RQA) enhancements

  • BSCAN Fallback for AXI Debug Hub for Versal
  • DFX Debug Support for ‘Insertion’ Flow – Versal 

PCIE subsystems

  • CPM5 x86 host drivers for Linux and DPDK
  • Improved performance in QDMA v5.0

Wired

  • DCMAC, HSC, QSGMII production on versal premium
  • Versal 400G RS-FEC with hard Interlaken on MRMAC FEC

Wireless

  • RFSoC DFE IP- New FT PRACH IP, Updated PRACH IP for multiband, Eval tool EoU enhancements
  • ORAN-PL resource reduction for Macro/Small cell
  • Enhancement multiband support

Memory

  • Versal HBMZE Public Access
  • HBM2E System C simulation

Infrastructure, Embedded, GT Wizards

  •  ECC enablement on soft CAN and AXI Stream FIFO

Multimedia

  • DisplayPort 2.1 Tx
  • HDMI 2.1 Compliance on ZU+
  • MPI CSI RX IP and DSP IP Enhancements
  • New MIPI CSI -2 RX example design on VEK280
  • VDU General Access 

Footnotes:
* Testing done by Vivado engineering team as of March 26th, 2023 on 45 Customer designs for Versal using the Vivado ML Software tool version 2023.1 running with IDR (Intelligent Design Runs) mode versus without (default mode). Results reflect a single test run of all designs, differences calculated and averaged. Actual results will vary due to factors including specific design, system configuration, and software versions. VIV-003
* Testing done by Vivado engineering team as of April 14th, 2023 on 50 Customer designs for UltraScale+ on Vivado ML software 2023.1 in IDR mode and without (default mode).    Results reflect a single test run of all designs, differences calculated and averaged. Actual results will vary due to factors including specific design, system configuration, and software versions. VIV-004

What's New in 2022.2 Key Highlights

  • Introducing Power Design Manager for Versal™ Adaptive SoC & Kria™ SOM
  • Intelligent Design Run now supported for Versal devices shows average 5% QoR improvement over explore strategy *
  • 1.4X compile time speed-up for UltraScale+™ architecture designs with Incremental Compile Flow **
  • Abstract Shell for DFX now supported for Versal devices and in project mode
  • DFX support enabled for Versal Premium SSI devices

Vivado ML What's New by Category

Expand the sections below to learn more about the new features and enhancements in Vivado™ ML 2022.2.

  • Devices enabled in the Enterprise Edition of Vivado ML 
    • Versal™ Premium Series: XCVP1702, XCVP1802, XCVP1102
  • Devices enabled in Standard and Enterprise Editions 
    • Kria™ SOM: XCK24
  • Devices that are production-ready
    • Versal Premium Series: XCVP1202
    • Versal Prime Series: XCVM1502
    • Versal AI Core Series: XCVC1702, XCVC1502

  • 25% reduction in peak disk footprint installation

​Infrastructure and Embedded​

  • Soft Endpoint Protection Unit (EPU) IP for protecting AXI agents residing in the PL​

Storage​

  • Embedded RDMA enabled NIC (ERNIC) now supports up to 2k Queue Pairs (QP)

Gigabit Transceiver (GT) Wizard

  • Versal GTMs now support rate switching between half and full density 
  • 16 configurations for Versal GTY/GTYP (limited to internal BRAM capacity)

Wired​

  • 100G Multi-rate Ethernet MAC Subsystems (MRMAC) 
    • Enabled 100G Ethernet 106G serial lane support
  • 600G Multi-rate Ethernet MAC Subsystem (DCMAC) 
    • Enabled 100GE, 200GE, 400GE 106G serial per lane support 
  • Aurora 64B/66B 
    • Added support for 16 lanes of GTYP or Gigabit Transceiver Module (GTM) on Versal Premium 

Wireless​

  • Zynq™ RFSoC DFE IP Update: Channel Filter and DUC-DDC UL/DL sharing 
  • Zynq RFSoC DFE DPD Update: PL resource reduction 
  • Zynq RFSoC DFE O-RU TRD: Updated w/ Low PHY processing only

PCIe® Subsystems 

  • CPM5 x86 host drivers for Linux and DPDK in public release on GitHub 
  • Versal CPM5 PCIe BMD Simulation Design (from CED Store) 
  • Versal CPM Tandem PCIe Design (from CED Store) 
  • QDMA v5.0 improved performance/resource utilization 

Multimedia 

  • Versal AI Edge enablement of soft IPs and Video Decoder Unit (VDU)
  • Warp Processor IP in production
  • Ultra HD 8K multimedia solution enablement for 
    • HDMI2.1
    • Video Mixer IP 

  • AXI streaming NoC MxN support in IP Integrator 
  • New address remap feature
  • Vivado for default syntax checking
  • Address path visualization
  • XML to JSON format for XCI files

  • Support for System Verilog “Interface Class”
  • Debug support for reference type System Verilog objects via tcl command and object window
  • VHDL-2008 support

  • Support for PCIe Debugger on new Versal architectures
    • VP1502
    • VP1702
    • VP1802
  • HBM2E Debugger support on Versal HBM devices
  • Integrated Bit Error Ratio Tester (IBERT) support on new Versal architectures
    • VP1502
    • VP1702
    • VP1802

  • QoR optimization for high fanout nets  
  • Placer replication for hard IP blocks 
  • Two new partitioning constraints for SSI designs  
  • LUT decomposition option to reduce congestion 
  • Incremental implementation enabled for monolithic Versal devices 
  • Support ECO flow for Versal devices 

  • New content added to QoR assessment report
  • Average 5% QoR improvement for Versal designs when Intelligent Design Runs is enabled 

  • DFX support for SSI devices 
  • Abstract Shell support for Versal Premium and Versal HBM devices 
  • Abstract Shell support for project-based mode 

Footnotes:
* Measurements are done by Vivado engineering team as of October 1st, 2022 on 48 Customer designs for Versal. Comparison is of Worst Negative Slack (WNS) on Explore Strategy vs. Intelligent Design on 2022.2 Vivado ML software tool. Actual improvement uplift for commercial systems may vary based on factors including system hardware, software and driver versions, and BIOS settings. 
** Measurements are done by Vivado engineering team as of October 1st 2022 on 68 designs comparing Default vs. Incremental compile on Vivado ML software tool 2022.2.  Six outlier compares in excess of 6x were discarded to provide a more representative performance average. 5% of design incrementally compiled for comparison. Actual improvement uplift for commercial systems may vary based on factors including system hardware, software and driver versions, and BIOS settings. 

Vivado ML What's New by Category

Expand the sections below to learn more about the new features and enhancements in Vivado™ ML 2022.1.

The following devices have been enabled both in the Enterprise Edition of Vivado ML

  • Defense-Grade Versal AI Core Series: XQVC1902
  • Space-Grade Versal AI Core Series: XQRVC1902
  • Versal AI Core Series: XCVC1702, XCVC1502
  • Versal AI Edge Series: XCVE1752
  • Defense-Grade Versal Prime Series: XQVM1802
  • Versal Prime Series: XCVM1402, XCVM1302, XCVM1502
  • Versal Premium Series: XCVP1202

The following devices have been enabled both in standard and Enterprise Edition

  • Artix UltraScale+: XCAU15P, XCAU10P
  • Zynq UltraScale+ MPSoCs: XAZU1EG

Wired

  • Versal Premium support:
    • 600G Ethernet Subsystem
    • 600G Interlaken with RS-FEC Subsystem
    • High Speed Crypto Engine (HSC) Subsystem
    • Aurora 64B/66B NRZ GTM
    • JESD204C 64B/66B GTM
  • Aurora 8B/10B supported in Artix UltraScale+ GTH
  • GTM 64G Ethernet PAM4 preset available
  • GTM XSR (Extra Short Range) preset available

  • ML Based resource estimation
  • Simpler format to user revision control
  • Module reference enhancement
    • Add Block Design as module reference into another BD
  • CIPS block automation now supports DDR and LPDDR simultaneously
  • Versal Hardblock planner in production in 2022.1

  • Slice in aggregates – VHDL 2008
  • Design unit name for SystemC in scope window

  • Design Methodology Violation Awareness
    • Popup warnings when opening a design with violations
  • Interactive QoR Assessment Report
    • Report QoR Assessment (RQA) score displayed in Design Runs
  • Easily Access Timing Closure Features in Projects
    • For Versal we now have ML Strategies and Intelligent Design Runs
  • Automatic QoR Suggestions Flow
    • Use when iterating designs with difficult-to-meet timing
  • Versal QoR Improvements Throughout Vivado
    • 5-8% average QoR improvement

  • IBERT and PCIe debugger support for Versal H10
  • Support for trigger at startup with Versal ILA and Storage qualification
  • Chipscopy enhancements

Vivado ML What's New by Category

Expand the sections below to learn more about the new features and enhancements in Vivado™ ML 2021.2.

The following devices have been enabled both in the Enterprise and Standard Editions of Vivado ML​

  • Artix UltraScale+ Devices: XCAU20P and XCAU25P

Timing and QoR Enhancements:

  • Provide support for users to input high-level throughput constraints​
  • Improve HLS timing estimation accuracy: When HLS reports timing closure, the RTL synthesis in Vivado should also expect to meet timing

Ease of Use Enhancements

Add interface adaptors report in the C synthesis reports:

  • Users need to know the resource impact that interface adaptors have on their design
  • Interface adaptors have variable properties that impact design QoR
  • Some of these properties have associated user controls which should be reported to users
  • Text version of bind_op and bind_storage reports are provided

Analysis & Reporting

The Function Call Graph Viewer has some new features:

  • New mouse drag based zoom in and out capability
  • New Overview feature that shows the full graph and allows the user to zoom in on parts of the overall graph
  • All functions and loops are shown along with their simulation data

A new Timeline Trace Viewer is now available after simulation. This viewer shows the runtime profile of your design and allows the user to remain in the Vitis HLS GUI.

  • Versal Premium GTM support 600G Interlaken preset​
  • Versal Premium GTM support for 100GE preset​
  • New Versal Premium Integrated 600G Interlaken Simulation Support​
  • EPC IP is now supported in Versal devices​
  • XPM Memory and XPM FIFO now support mixed RAM mode,​
    using 'ram_style = "mixed"'​
  • Lossless Compression IP added support for an enhanced decompression mode, doubling throughput for an added LUT cost​
  • Released PCIe Subsystems support for Artix UltraScale+ FPGAs​
  • Expanded PCIe Subsystems device support for Versal Adaptive SoCs

Intelligent Design Runs (IDR)

  • Improved reporting content: 
    • Removed irrelevant table entries and inactive links
    • Added design statistics for all stages
  • Bitstream generation available as a right-click menu selection
  • Terminate runs available as a right-click menu selection

ML-based placer directive prediction

  • Up to 3 top-performing placer directives are predicted at place_design run time
  • Use place_design -directive option with values: Auto_1, Auto_2, and Auto_3

Vivado ML What's New by Category

Expand the sections below to learn more about the new features and enhancements in Vivado™ ML 2021.1

  • Versal™ AI Core Series: - XCVC1902 and XCVC1802​
  • Versal Prime Series: - XCVM1802​
  • Virtex™ UltraScale+™ HBM device: XCVU57P

  • Flexlm version upgraded to 11.17.2.0
    • Support 64-bit versions of Linux and Windows only​
    • Customer using floating license must upgrade licensing utilities to Flexlm 11.17.2.0​

  • Block Design Container
    • 2021.1 is the production release for block design containers.
    • Enables Modular Designing for Reusability​
    • Allows Team Based Designs​
    • Enables DFX Flow in the Project Mode​
    • Ability to specify variants for simulation and synthesis
    • Address management for BDCs from the Top-level BD
       
  • Vivado Store​
    • Download boards and example designs from GitHub​
    • 3rd party board partners can contribute to these repositories asynchronously to Vivado releases
       
  • IP/IPI Revision Control Improvements​
    • Migration of older Vivado projects to new directory structure
       
  • CIPS 3.0​
    • IP Re-architecture of CIPS to Hierarchical Model​
    • New Modular User Interface

  • Vivado Text Editor – Sigasi Backend​
    • Language protocol server supporting:​
      • Autocomplete​
      • Go to Definition / Find Usages​
      • Tool-tips​
      • Indent (Range only in VHDL)​
      • Syntax Errors and Warnings as you type​
      • Code folding​
      • Semantic Highlighting

  • IPI Designer Assistance for CIPS & NoC​
    • Enables intuitive Block Automation for NoC & CIPS connectivity​
    • Allows easier creation of designs that access all available memory connected to the device or on the board, e.g. DDR and LPDDR

  • Non-Power of 2 DDR Assignment through Interconnect​
    • IPI now supports non-power-of-2 (NPOT) address assignments across Address Paths with one or more SmartConnect IP​

  • IP Packager Enhancements​
    • Packager customer experience improvements​
      • Connectivity of custom interfaces in IPI / Custom IP​
      • XPM memory in the packager​
      • Ability to tag files as SV or VHDL-2008 in the packager from package an IP from a directory​
    • Production release for packaged RTL IP as Vitis kernel​
      • Kernel specific DRCs within IP packager​
      • Ease of use
      • Preservation of metadata in these packaged IPs for Vitis kernel usage
  • IP Enhancements ;– Data Center​
    • PCIe Subsystems​
      • Early access support for CPM5, PL PCIE5, and GTYP in Versal Premium​
      • CPM4 support in Versal CIPS Verification IP (VIP) for simulation​
    • Introducing the Algorithmic CAM IP​
      • EA for US+ devices​
    • AXI IIC improvement to dynamic read mode function​
    • SmartConnect support for non-power-of-two address ranges​
    • XilSEM library API release & documentation in UG643​
    • SEM IP core device support additions for US+ devices
  • IP Enhancements – Video and Imaging​
    • Video and Image Interface IPs​
      • CSI TX subsystem adds support for YUV422 10bit​
      • DisplayPort Subsystems add support for HDCP2.2/2.3 repeater feature​
      • HDMI2.1 (controlled access) adds support for Dynamic HDR, and enhanced gaming features (VRR, FVA, QMS and ALLM)​
    • New IP: Warp Processor for digitally manipulating images
      • Supports Keystone distortion, Barrel and Pincushion distortions and Arbitrary distortions​
      • Scaling: 0.5x, 1x, 2x; Rotation: -90 to +90 deg​
      • Resolutions from 320x240 to 3840x2160, with multichannel support​
      • Input and Output: 8/10/12 bpc YUV, RGB
  • IP Enhancements - Wired
    • 100G Multirate Ethernet Subsystem - MRMAC
      • 10G/25G/40G/50G/100G Ethernet NRZ GTM
      • MRMAC 25G Ethernet at –1LP​

  • IP Enhancements – Wireless
    • O-RAN​
      • Static/Dynamic Compression/Decompression Function in the IP core (BFP + Modulation)​
      • New interface to support LTE Section Extension Type 3 information and feed an external LTE precoding block through a single interface​
      • Support for Beam ID mapping per Slot (in addition to existing per Symbol method)​
      • Support for DL Section Type 3 messages​
      • Section Type 0 added to PDxCH BID port​
      • Max Ethernet packet size increased to 16000 bytes (Support for 9600 byte jumbo frames)​
  •  IP Enhancements – Storage​
    • NVMeHA now supports Versal and VU23P devices​
    • NVMeTC now supports Versal and VU23P devices​
    • ERNIC now supports Versal​
      • Native connection to the MRMAC​
    • AES-XTS available only by special request
  • IP Enhancements XPM
    • XPM_Memory and EMG now support all URAM sizes​
    • XPM_Memory and EMG now support mixed RAM combinations​
      • Use ram_style = "mixed"​ 
    • XPM_Memory and XPM_FIFO allow disabling of assertions for broader simulation support​
      •  DISABLE_XPM_ASSERTIONS define has been added
  • IP Enhancements - GT Wizard 
    • Versal GTY Wizard Production
    • Versal GTYP Wizard available as EA
    • Versal GTM Wizard available as EA    

  • Vitis HLS 2021.1 – Production Versal Support ​
  • Versal timing calibration and new controls for DSP block native floating-point operations​
  • Flushable pipeline option with lower fanout logic (free running pipeline a.k.a. frp)
  • Enhanced automatic memory partitioning algorithm and new config_array_partition option​
  • New “Flow Navigator” in GUI and merged views for synthesis, analysis and debug​
  • Vitis flow “never ending” streaming kernel support for low runtime overhead​
  • Function call graph viewer with heatmap for II, latency and DSP/BRAM utilization​
  • New synthesis report section for BIND_OP and BIND_STORAGE​
  • Improved data-driven pragma handling for better consistency​
  • Vivado report and new export IP widgets to pass options to Vivado​
  • New text report after C synthesis to reflect GUI information

ML model Integration

  • Machine Learning models to predict and select optimizations​
    • 30% compilation speedup for Versal designs

New Synthesis Features​

  • XPM_MEMORY supports heterogeneous RAM mapping​
    • Memory array mapped using all device resource types: UltraRAM, Block RAM, and LUTRAM​
    • Most efficient use of all resources​
    • Use parameter or generic: MEMORY_PRIMITIVE(“mixed”)​
    • Does not support WRITE_MODE = NO_CHANGE​
    • VHDL-2008: new support for the to_string() function​
    • Log report includes RTL overrides of IP generics and parameters

Machine Learning models in implementation​

  • Predict routing congestion and route delays​
  • Better correlation between placement-based estimation and actual routing a better Fmax and reduced compile times​

opt_design -resynth_remap​

  • New timing-driven logic cone resynthesis optimizations that reduce logic levels​

Manually retime LUTs and registers during placement with XDC properties​

  • PSIP_RETIMING_BACKWARD​
  • PSIP_RETIMING_FORWARD

New Features for Versal Devices​

  • Calibrated Deskew adjusts the clock network delay taps before device startup to further minimize skew​
  • Automatic pipeline insertion improves clock speed by on paths…​
    • Between PL and NoC and between PL and AI Engines
    • Available both from the AXI Regslice IP and by using auto-pipeline properties​
    • Adds latency to pipelined paths​
  • Elastic pipelines from shift register primitives (SRLs)
    • pipelines are built around an SRL which holds excess pipeline stages​
    • Placer builds the ideal pipeline based on source and destination placement
    • Stages can be pulled out of the SRL to cover a wider distance​
    • Stages are absorbed by the SRL to shrink the pipeline for shorter distances​
    • Preserves latency on pipelined paths

Intelligent Design Runs:

  • Intelligent Design Runs (IDR) gives pushbutton access to a new, powerful automated timing closure flow
    • report_qor_suggestions​
    • ML strategy prediction​
    • Incremental Compile​
  • Available in Vivado projects and is launched by a right-click menu selection of an implementation run that fails timing. The IDR Reports dashboard details the flow progress and provides hyperlinks to the related reports.​A great option for users with timing closure difficulty​
    • QoR gain average >10%

Report QoR Suggestions (RQS) Improvements​

  • DFX-aware QoR suggestions​
    • Suggestions given only on DFX modules when static is locked​
    • No suggestions that disrupt DFX boundaries​
    • Synthesis suggestions correctly scoped to global or out-of-context runs
  • Assessment included in the interactive report_qor_suggestions (RQS) GUI report

Methodology Violations in Timing Reports​

  • Timing reports now include Report Methodology summary​
    • Draws attention to methodology violations​
    • Neglected methodology violations may cause timing failures​
  • Includes the summary of the methodology violations from the latest report_methodology run​
    • Methodology violations summary stored with design checkpoint

New Constraint Reporting Features​

  • report_constant_path: new command to identify the source of constant logic values observed on cells and pins​
    • report_constant_path <pins_or_cells_objects>​
    • report_constant_path -of_objects [get_constant_path <pins_or_cells_objects>]

DFX for Versal

  • Versal DFX flows available with production status​
    • Compile DFX designs from block designs to device image creation​
    • Use Vivado IPI Block Design Containers (BDC) for creating Versal DFX designs​
  • Leverage DFX IP in Versal just as with UltraScale, UltraScale+​
    • DFX Decoupler IP, DFX AXI Shutdown Manager IP to isolate non-NoC interfaces​
  • All programmable logic is partially reconfigurable​
    • From NoC to clocks to hard blocks​
  • AIE full array Dynamic Function eXchange support​
    • Supported through Vitis platform flows

BDC for DFX

  • Block Design Containers (BDC) for DFX released in IP Integrator​
    • Supports all architectures, critical for Versal​
  • Place a block design within a block design to create and process DFX designs​
    • UG947 shows IPI BDC tutorials for Zynq UltraScale+ and Versal devices​
    • More DFX tutorials to be posted on GitHub

Classic SoC Boot Flow Using DFX​

  • Classic SoC Boot flow available for Versal designs​
    • Enables users to quickly boot their DDR-based processing subsystem and memory to run Linux prior to loading the programmable logic​
    • Separate programming events in Versal to emulate the Zynq boot flow​
    • Auto-Pblock generation used in this flow​
    • Not compatible with CPM

Versal Tandem configuration for CPM4

  • Tandem PROM and Tandem PCIe® for CPM4 available​
  • Users who require 120 ms configuration of a PCIe end point now have a selection in
    the CIPS customization GUI to select the Tandem Configuration mode​
    • Tandem PROM – load both stages from flash​
    • Tandem PCIe – load stage 1 from flash,
      stage 2 over PCIe link via DMA​
    • None – standard boot

​Abstract Shell Support for Nested DFX Designs in UltraScale+

  • Subdivide your Reconfigurable Partition (RP) into multiple nested RPs using Nested DFX (pr_subdivide)​
  • Create Abstract Shell for each nested RP (write_abstract_shell)​
  • Accelerate the implementation of each Nested RP by using its Abstract Shell

  • VHDL-2008 Enhancements
    • Unconstrained Arrays​
    • ·Conditional Operators​
    • Unary Reduction Operators​
       
  • Code Coverage Support​
    • write_xsim_coverage command support for writing intermediate coverage database

SmartLynq+ module

  • Optimized for Versal High-Speed Debug Port (HSDP)​
    • Faster device programming & Memory access
    • High speed data upload & download​
    • Data storage: 14GB DDR memory on module​
  • High-Speed Debug Port (HSDP) Support​
    • Support for connecting to Aurora based HSDP over USB-C connector​
  • PC4 and USB based JTAG​
  • Serial UART support

ChipScopy

  • Open-Source Python API for ChipScope​
    • Control and communicate with Versal Device and Debug Cores​
    • Vivado not required to use – just need a PDI/LTX​
    • Benefits​
      • Build custom debug interfaces​
      • Interface with python ecosystem​