Overview
With a streamlined design flow, Vivado Design Suite enables traditional FPGA developers to achieve design closure quickly with Versal adaptive SoCs
Meet FMAX Targets
New P&R and clocking algorithms let designers meet timing for the most complex designs
Fast Compile & Flexible Boot
Reduce compile time1,2 and boot the PS first for fast design closure and system bring-up
Top-Level RTL Flows
Use traditional RTL flows to unlock system performance on Versal devices
Streamlined Design Flow for Hardware Developers
*Applies only to devices with AI Engines.
Migrate to the Versal Architecture in Five Steps with the Vivado Design Suite
The AMD Versal™ adaptive SoC architecture delivers heterogeneous acceleration and hard IP integration for breakthrough system performance per watt. But how do you ensure optimal results when migrating from previous-generation FPGAs? Follow these best practices to streamline your transition using the AMD Vivado™ Design Suite.
Meet FMAX Targets
Proven FPGA Methodologies
Versal™ adaptive SoCs enable a new paradigm of system design while building on proven FPGA methodologies. Capabilities within the Versal architecture and Vivado Design Suite to achieve timing closure include:
- Compilation flows that reduce routing congestion
- Auto-calibration of clock regions to minimize clock-skew
- New clock buffer technology for targeted skew reduction
- Enhanced die-to-die connectivity for SSIT-based devices
The latest enhancements in Vivado tools coupled with built-in silicon features enable both automation and user control to meet timing closure.
Performance Improvement Vivado 2024.1 vs 2024.2
Versal Monolithic Devices³
4.5%
Average Performance Improvement
2024.2
Versal SSIT-based Devices⁴
4.7%
Average Performance Improvement
2024.2
Performance calculated using the worst-case negative slack (WNS) of the clocks in the design.
Maximizing Fabric Performance (FMAX)
View webinar and download the presentation to explore RTL techniques, implementation strategies, and features within the Vivado Design Suite to meet fabric performance on Versal devices.
Fast Compile and Flexible Boot
Up to 2X Compile Time Reduction1,2
Versal™ adaptive SoCs provide greater logic resources and hard IP for more complex designs. But with increased complexity comes potentially long compile times. Vivado™ Design Suite now features the Advanced Flow to accelerate compilation by up to 2X over previous releases with enhancements at every implementation stage:
✓ Automatic partitioning for parallel place and route
✓ Smarter placement to reduce congestion
✓ Advanced routing algorithms for faster timing closure
Compile Time Improvements1,2
SSIT-Based Devices
Monolithic Devices
Fast Compile Overview
Discover how the Vivado Design Suite uses hierarchical design optimization and multi-threading to minimize compile times. Watch the video and download the presentation for key insights and real-world implementation strategies.
Flexible Processor Boot
The Vivado Design Suite provides options to configure the processing system to boot first for applications that need fast OS startup, strict power sequencing control, or dynamic reconfiguration of the PL without interrupting software runtime. The new Segmented Configuration flow:
- Boots processors, memory, and OS first
- Defers PL configuration to a later stage
- Delivers a PL PDI (config file) via Linux® or U-Boot at runtime
Segmented configuration is available as an early access (EA) feature in the 2024.2 release. Please refer to the GitHub tutorials for more details.
2-Phase Boot Sequence for Fast Device Bring-Up
Image Zoom
Flexible Boot Overview
Discover why the Versal™ SoC boot process is divided into two phases and how it accelerates system bring-up. This video breaks down key architectural blocks in the boot process and provides a step-by-step approach to achieve optimal results.
Top-Level RTL Flows
With Versal adaptive SoCs, hardware developers can map their designs using a block-based system approach using IP Integrator or stay in their top-level RTL for ease of migration of previous generation FPGA designs using two new features:
- The modular NoC flow eases design entry by allowing instantiation via RTL and IP integrator environments using a system level approach.
- The new Versal transceivers wizard provides an RTL wrapper created around GT primitives and allows for basic customization.
While IP integrator is still leveraged for various IP blocks in the Versal adaptive SoC flow, the top-level RTL flow allows for flexibility of importing designs with complex topologies.
Top-Level RTL Flows
Learn how the modular NoC and new transceiver wizard simplify design entry for RTL designs, enabling traditional FPGA flows while leveraging the benefits of Versal hard IP.
New Design Migration Course
Migrating from AMD UltraScale+™ devices to Versal adaptive SoCs
If you’re starting from an UltraScale+ FPGA or adaptive SoC design, this on-demand course provides strategies for system planning, partitioning methodologies, and migration best practices for diverse system architectures. Streamline your transition to Versal adaptive SoCs and enroll today!
Resources
Versal Knowledge Base and organized by the stage of your design. Including documentation, training modules, training courses, and more.
Vivado 2024.2 Release
Download the latest release of the Vivado Design Suite to access the latest features
Power Design Manager 2024.2 Release
Download the latest release to ensure accurate power data for UltraScale+ and Versal devices
Contact Us
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Footnotes
- Based on a single-test scenario performed by AMD in December 2024, measuring the average compile times (hours/minutes) over 124 designs targeting Versal Stacked Silicon Interconnect (SSI) technology devices using Vivado Design Suite 2024.2 vs. Vivado Design Suite 2024.1. Compile time results will vary based on device, design, configuration, and other factors (VIV-011)
- Based on a single-test scenario performed by AMD in December 2024, with measuring the average compile times (hours/minutes) over 151 designs targeting Versal monolithic devices using Vivado Design Suite 2024.2 vs. Vivado Design Suite 2024.1. Compile time results will vary based on device, design, configuration, and other factors. (VIV-010)
- Based on AMD worst negative slack performance testing in April 2025, using Vivado Design Suite 2024.2 vs. 2024.1. Stated results are a geomean average over 153 monolithic designs. Results may vary based on device, design, configuration, software, and other factors (VIV-013)
- Based on AMD worst negative slack performance testing in April 2025, using Vivado Design Suite 2024.2 vs. 2024.1. Stated results are a geomean average over 125 SSI designs. Results may vary based on device, design, configuration, software, and other factors (VIV-014)
Footnotes
- Based on a single-test scenario performed by AMD in December 2024, measuring the average compile times (hours/minutes) over 124 designs targeting Versal Stacked Silicon Interconnect (SSI) technology devices using Vivado Design Suite 2024.2 vs. Vivado Design Suite 2024.1. Compile time results will vary based on device, design, configuration, and other factors (VIV-011)
- Based on a single-test scenario performed by AMD in December 2024, with measuring the average compile times (hours/minutes) over 151 designs targeting Versal monolithic devices using Vivado Design Suite 2024.2 vs. Vivado Design Suite 2024.1. Compile time results will vary based on device, design, configuration, and other factors. (VIV-010)
- Based on AMD worst negative slack performance testing in April 2025, using Vivado Design Suite 2024.2 vs. 2024.1. Stated results are a geomean average over 153 monolithic designs. Results may vary based on device, design, configuration, software, and other factors (VIV-013)
- Based on AMD worst negative slack performance testing in April 2025, using Vivado Design Suite 2024.2 vs. 2024.1. Stated results are a geomean average over 125 SSI designs. Results may vary based on device, design, configuration, software, and other factors (VIV-014)