Proven Path to Fast Design Development

Accelerate design and implementation for AMD Spartan™ UltraScale+™ FPGAs using the AMD Vivado™ Design Suite—an easy-to-use, integrated, and free toolchain. Unlock high I/O, low power, and robust security features in the latest Spartan family—without complexity.

Unified Flow

Integrated toolchain for simulation, synthesis, place & route, and debug

Push-Button Timing Closure

Meet FMAX targets using a push-button flow—with proven performance

Broad Selection of IP Cores

Broad selection of nearly 400 soft IP cores along with seamless integration of new hard blocks in Spartan UltraScale+ FPGAs

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Unified Flow for Fewer Design Iterations

The Vivado Design Suite eliminates the need for multiple tools, enabling fewer iterations and easier debug. Designers benefit from an all-in-one flow for Spartan UltraScale+ FPGAs, accelerating full design cycles and small updates.

  • Integrated toolchain: Simulation, synthesis, place & route, and debug in one cohesive flow
  • Advanced features: Best-in-class QoR and timing analysis

Watch this step-by-step video tutorial to jumpstart your Spartan UltraScale+ FPGA project. Learn how to build a real application and navigate the Vivado tool flow—from design entry to the integration of new hard blocks, implementation, and debug.

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Push-Button Timing Closure

For Spartan UltraScale+ FPGAs, the Vivado Design Suite helps you meet your performance targets with a push-button flow—reducing trial-and-error constraint tuning and the need to move to higher-cost speed grades to meet timing.

  • The AMD Vivado Design Suite 2025.1 and Spartan UltraScale+ SU35P FPGA offer an average 92% pass rate at up to 250 MHz using a push-button flow with no design changes1
  • Optimized implementation: Leverage pre-tuned place & route strategies—without the need for deep tool expertise or manual tuning
  • Projected up to 30% less power vs. previous generation2
Spartan UltraScale+ (SU35P) Designs Meeting Timing with Push-button Flow
SU35P at -1 (slowest) Speed Grades
97.8%
91.3%
80.4%
0
20
40
60
80
100
120
150 MHz
200 MHz
250 MHz

SU35P Target Frequency

SU35P at -2 (fastest) Speed Grades
97.8%
95.1%
84.4%
0
20
40
60
80
100
120
200 MHz
250 MHz
300 MHz

SU35P Target Frequency

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Broad Portfolio of Hard and Soft IP

Accelerate the design process with a rich library of pre-verified IP—combining hard blocks in the Spartan UltraScale+ FPGA with a portfolio of soft IP from the Vivado catalog. With a streamlined integration flow, you can focus more on your application and less on building infrastructure from scratch.

  • Accelerated design cycles: Leverage ready-made infrastructure IP
  • Focus on differentiation: Spend effort where it matters—your application
  • New hard IP: DDR4, PCIe® Gen4, and security blocks
  • Soft IP: Nearly 400 cores to jumpstart your design
  • Streamline integration of hard and soft cores with the Vivado IP integrator 
Explore the IP Catalog
AMD Vivado™ Design Suite for AMD Spartan™ UltraScale+™ FPGAs solution rief cover
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Resources

Webinars and How-To Videos
All Vivado for Spartan UltraScale+ Videos
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Power Design Manager

Next‑generation, stand‑alone power estimation tool for AMD Versal, UltraScale+, and Kria™ designs—accurate early budgeting.

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Vivado™ Design Suite

Adaptive FPGA/SoC design suite from AMD—top-tier synthesis, implementation, dynamic IP, power/timing closure, free & enterprise.

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Footnotes
  1.  VIV-018
    Based on worst-negative slack testing by AMD in July 2025, on a Spartan UltraScale+ SU35P FPGA with Vivado Design Suite 2025.1, tested at -1 (slowest) speed grade at (150 MHz–250 MHz) over 46 designs and at -2 (fastest) speed grade at (200 MHz–250 MHz) over 41 designs. Results will vary based on device, design, configuration, and other factors.
  2. SUS-003
    Projection is based on AMD labs internal analysis in January 2024, using Total Power calculation (Static plus Dynamic power) based on the difference in logic cell count of an AMD Artix UltraScale+ AU7P FPGA, to estimate the power of a 16 nm AMD Spartan UltraScale+ SU35P FPGA versus a 28 nm AMD Artix 7 7A35T FPGA, using Xilinx Power Estimator (XPE) tool version 2023.1.2. Actual Total Power will vary when final products are released in market, based on configuration, design, usage, and other factors.